Memory access time

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Cyprian
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Re: Memory access time

Postby Cyprian » Fri Sep 26, 2014 10:15 pm

awesome story Marty. thanks
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Re: Memory access time

Postby calimero » Thu Jun 22, 2017 12:47 am

Cyprian wrote:
But there is one interesting feature - FUNNEL chip. I read somewhere (maybe in Profibuch) that in a specific situation it can works as a 64bit cache for read cycles.


I just found this article: http://www.stcarchiv.de/stc1990/10_ataritt.php

They claim that ST-RAM is ALWAYS read and write in 64bit so basicly you got next long word for free! :)

They also claim that TT RAM cycles are far from optimal (but in line that you already measure: around 7MB/s):

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Re: Memory access time

Postby AtariZoll » Thu Jun 22, 2017 8:32 am

calimero wrote:I just found this article: http://www.stcarchiv.de/stc1990/10_ataritt.php
They claim that ST-RAM is ALWAYS read and write in 64bit so basicly you got next long word for free! :)
They also claim that TT RAM cycles are far from optimal (but in line that you already measure: around 7MB/s):
]

TT RAM is 64-bit, so any access to it is access to all 64 bits . That was necessary because higher video modes, as it is stated already here. But poor CPU is only 32-bit, so it can access to only half of RAM bus. There must be multiplexer what switches proper half to CPU data bus. Actually, it is more complicated, since there are 8 and 16 bit accesses to RAM too .
But that claim about next long for free stays only if you accessing lower half of 64-bit (8 bytes), so if address is mod 8 (dividable by 8) - then no need to read RAM again for upper half. It is there already. If accessing upper half, next long will need new RAM access.
What is possible gain ? Instead 500nS 62.5 nS - what would be best RAM access cycle time of 32-bit , 32 MHz 68030 . But logic what does all it optimally for all accesses must be quite complex, and what is done in TT some 28 years ago is simpler, I guess.
This makes me think following: if CPU just accessing RAM when video accessing it not, then instead 500nS, only 250nS would be enough. And chance for that is: not 1/2, since it must be at exact start of 250nS RAM cycle, but much less - 1/8 considering that 62.5 nS. So, I guess that TT designers just did not use that opportunity - too much complication for small gain.
Here to add, that in ST it is much simpler: CPU's best RAM access cycle is 500nS.
Famous Schrodinger's cat hypothetical experiment says that cat is dead or alive until we open box and see condition of poor animal, which deserved better logic. Cat is always in some certain state - regardless from is observer able or not to see what the state is.

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Re: Memory access time

Postby calimero » Thu Jun 22, 2017 1:21 pm

btw I am making Google spreadsheet table with all benchmarks...

take a look here: https://docs.google.com/spreadsheets/d/ ... sp=sharing

if you would like to edit it, please let me know! (you will need gmail account)
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Re: Memory access time

Postby Cyprian » Thu Jun 22, 2017 2:17 pm

AtariZoll wrote:Here to add, that in ST it is much simpler: CPU's best RAM access cycle is 500nS.


in both machines - ST and TT, access to the ST ram works in exactly the same manner. One memory slot is equal 250ns and CPU gets even memory slots, Shifter odd.
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Re: Memory access time

Postby calimero » Thu Jun 22, 2017 4:06 pm

Cyprian wrote:
AtariZoll wrote:Here to add, that in ST it is much simpler: CPU's best RAM access cycle is 500nS.


in both machines - ST and TT, access to the ST ram works in exactly the same manner. One memory slot is equal 250ns and CPU gets even memory slots, Shifter odd.

but how Atari TT have 4 times bigger resolutions if ST-ram access have same timings?
Because Shifter in TT access ST-Ram by 64bit width and in ST only by 16bit width.
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Re: Memory access time

Postby AtariZoll » Thu Jun 22, 2017 4:45 pm

calimero wrote:
Cyprian wrote:
AtariZoll wrote:Here to add, that in ST it is much simpler: CPU's best RAM access cycle is 500nS.


in both machines - ST and TT, access to the ST ram works in exactly the same manner. One memory slot is equal 250ns and CPU gets even memory slots, Shifter odd.

but how Atari TT have 4 times bigger resolutions if ST-ram access have same timings?
Because Shifter in TT access ST-Ram by 64bit width and in ST only by 16bit width.

Exactly.
Famous Schrodinger's cat hypothetical experiment says that cat is dead or alive until we open box and see condition of poor animal, which deserved better logic. Cat is always in some certain state - regardless from is observer able or not to see what the state is.

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Cyprian
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Re: Memory access time

Postby Cyprian » Thu Jun 22, 2017 4:53 pm

AtariZoll wrote:
calimero wrote:
Cyprian wrote:
in both machines - ST and TT, access to the ST ram works in exactly the same manner. One memory slot is equal 250ns and CPU gets even memory slots, Shifter odd.

but how Atari TT have 4 times bigger resolutions if ST-ram access have same timings?
Because Shifter in TT access ST-Ram by 64bit width and in ST only by 16bit width.

Exactly.


yep
ST Shifter <-- 16bit bus <-- RAM
TT Shifter <-- 64bit bus <-- RAM
Portfolio / Lynx II / Jaguar / TT030 / Mega STe / 800 XL / 1040 STe / Falcon030 / 65 XE / 520 STm / SM124 / SC1435
SDrive / PAK68/3 / Lynx Multi Card / LDW Super 2000 / XCA12 / SkunkBoard / CosmosEx / SatanDisk / UltraSatan / USB Floppy Drive Emulator / Eiffel / SIO2PC / Crazy Dots / PAM Net
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