Pro VME Hypercache 030

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Arne
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Pro VME Hypercache 030

Postby Arne » Fri Apr 04, 2014 6:44 pm

I've got a ProVME Hypercache030 that I bought once with a MST. It's a 68030 speeder with 16kByte L2 Cache and 4 TOS ROMs on-board.
What always puzzled me was how they manage the L2. I mean PAK68/3 has those TagRAMs IDT71S74, but this one hasn't. It's got plenty of 74xxx and GALs. Does anyone know how this (probably direct mapped cache) is accessed? How does the Hypercache know that if specific data word is stored in the L2 or not? As I see this is the job of these TagRAMs. How did Pro VME without?

And does anyone have a description of the expansion port to the right?

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Re: Pro VME Hypercache 030

Postby DarkLord » Sat Apr 05, 2014 4:34 am

Wow, honestly that is, I believe, the first time I've ever heard of this card.

Was it only released in the German market? Love to have more specs on it.

Do you have the owners manual/installation instructions?

Thanks.
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Re: Pro VME Hypercache 030

Postby Arne » Sat Apr 05, 2014 7:54 am

I just have the PCB. There is not much installation at all. Unsolder the 68000, put a socket at its place and put the HC030 in that socket. Finished.

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Re: Pro VME Hypercache 030

Postby DarkLord » Sat Apr 05, 2014 12:22 pm

Nice. Sorry I couldn't offer any useful advice about it though.
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Re: Pro VME Hypercache 030

Postby Arne » Mon Feb 04, 2019 10:00 am

I found the accelerator card in one of my drawers these days. Anybody able to answer my questions? There are 10 74HCT573 latches between the 68000 and the FPU socket and 8 MCM6168P55 (4K x 4 55ns SRAMs to my knowledge) between TOS EPROMs and CPU/FPU. The ICs with stickers are 16V8/22V10.
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Re: Pro VME Hypercache 030

Postby SteveBagley » Mon Feb 04, 2019 11:54 am

Arne wrote:How does the Hypercache know that if specific data word is stored in the L2 or not? As I see this is the job of these TagRAMs. How did Pro VME without?


TAG RAM is just static RAM with integral comparators that compare the data stored in memory with the data on the data bus to see if they are equal or not. In a cache setting, the TAG ram is used to store part of the address (the cache 'tag') that is stored at that location in the cache (the actual data is stored in a separate piece of normal static RAM). I imagine this card is doing the same using part of normal static RAM to store the 'tag' and part to store the data except the comparison is being done inside the PALs/GALs.

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Re: Pro VME Hypercache 030

Postby Arne » Mon Feb 04, 2019 1:10 pm

Thanks for the explanation on Tag. But I know that already! I dug into the Mach16 schematic and IDT datasheet some years ago. Besides I've studied Computer science. Anyway: I looked into the topic of creating a TagRAM with standard Static RAM and external logic two years ago. Problem is that IMO many bus cycles are wasted on investigation if the Tag address is stored or not. And the external logic has to drive the static RAMs. But the most daunting reason doing so is the amount of time it would take to do the comparison. The IDTs do this in ~30ns.
IMHO the L2 wouldn't be much faster than main memory. But I could be wrong here. At least it takes considerably more time than the IDTs need.
BTW: if the eight 4K x4 SRAMs are wired in a way that they connect directly to the D[0..31] of the 68030 this would counteract your explanation that these are used for storing data and Tag. Would it not?

Thanks anyway as your statements about the Tag are absolutely correct.
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Re: Pro VME Hypercache 030

Postby Arne » Mon Feb 04, 2019 2:43 pm

Some side notes. I thought that the Hypercache 030 boots into KAOS but seems to contain a patched 1.04
The bootscreen is pretty interesting as it contains the address of the Bavarian Broadcasting in Munich!

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Desktop info gives this:
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Unfortunately Sysinfo bombs out with two bombs. At least the 58234 Bytes version.
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Re: Pro VME Hypercache 030

Postby Arne » Mon Feb 04, 2019 3:02 pm

Case closed. I should have checked more thoroughly :oops:
Beneath three of the four ROM sockets are three MK41H80 Tag RAMs.
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Re: Pro VME Hypercache 030

Postby SteveBagley » Mon Feb 04, 2019 4:04 pm

Arne wrote:Case closed. I should have checked more thoroughly :oops:
Beneath three of the four ROM sockets are three MK41H80 Tag RAMs.


Heh :) Saves me typing out an explanation of how it works using just static RAM (at the expenses of a few wait states)

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Re: Pro VME Hypercache 030

Postby Arne » Mon Feb 04, 2019 4:21 pm

SteveBagley wrote:Heh :) Saves me typing out an explanation of how it works using just static RAM (at the expenses of a few wait states)

Steve


I'd read it with delight. Always eager to learn something new :D

If someone with this accelerator looks for drivers: I have put a ZIP into the Downloads section of my homepage.
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Re: Pro VME Hypercache 030

Postby Arne » Mon Feb 04, 2019 5:03 pm

Did a little sketch.

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Cacheable area: 4MB
Cache size: 64KB
Given that the DataSRAM (not on sketch) is 64KByte in size A[15..2] are connected to the address pins of the SRAM used for storing the Tag. So A[21..16] form up the Tag that needs to be stored/read. So these address bits are connected to the data I/Os of the TagSRAM.
On a write the address is always stored in the TagRAM (red) and on reads the stored Tag (green) is compared to the actual A[21..16]. This results in the MATCH being active or not. This is just a very rough collection of thoughts and is not complete.

Steve do you agree?
Last edited by Arne on Mon Feb 04, 2019 5:09 pm, edited 1 time in total.
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Re: Pro VME Hypercache 030

Postby dhedberg » Mon Feb 04, 2019 5:05 pm

Wow, pretty awesome upgrade for a Mega ST. Is the CPU clocked at 8MHz? Would be interesting to see some benchmarks (comparing it to a MegaSTe), depending on the clock frequency of the CPU it might beat a MegaSTe considering it's a 68030 CPU.
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Re: Pro VME Hypercache 030

Postby Arne » Mon Feb 04, 2019 5:28 pm

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Re: Pro VME Hypercache 030

Postby dhedberg » Mon Feb 04, 2019 8:12 pm

Thanks for the links. Interesting read. Seems like a great card for the MegaST. Was fairly expensive back in the days.
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