In case someone is interested...
I have made an 8MB Alt-RAM + TOS 2.06 upgrade for my MegaST-4, giving a total of 12 MB of system memory. The purpose of the exercise was to make a reasonably simple upgrade at low cost, using only standard TTL chips, because I do not have the resourecs to handle programmable chips. Although undoubtedly much better Alt-RAM boards have been designed and produced (i.e. the MagnumST) they are not within my reach- and, besides, it was fun to design this thing, because electronics is not my profession, just a hobby.
The design was based on an 8MB RAM upgrade for Amiga, proposed in 1992 by John Kamchen (thanks to Lyndon Amsdon for pointing to that circuit). I suppose that my design is sufficiently similar to the original one (four logic chips and two EPROMs added) so that, eventually, the PCB layout provided for the Kamchen's circuit might be adapted.
The board uses eight 30-pin 1MB SIMM/SIPP modules. AFAIK the logically equivalent 8MB 72-pin modules, or any other having 10 multiplexed-address lines can be used. The memory chips used should have CAS-before-RAS refresh capability (not all SIMM modules had this feature, but all those those with 8 or 9 1MBit chips should be safe to use).
Address space of the board starts at $600000, so there is a 2MB "memory hole" between this address and ST-RAM which serves (without any additional provisions) to prevent TOS from confusing this memory with ST-RAM at boot time. Either 2, 4, 6 or 8 MB can be installed at 2MB address intervals.
A pair of 256KB EPROMs on the board contain TOS 2.06 and Magic 6.2, which can be selected, as well as the on-motherboard TOS 1.4, by a three-position switch. A pair of 128KB EPROMs could be used as well, contianing only one OS, of course. Without any changes, or with some trivial changes in design, EPROMs should be replaceable with a pair of pin-compatible 128KB static-RAM chips. If SRAMs with "sleep mode" are used, a rechargeable-battery backup could be installed so that the SRAM chips would hold the OS practically indefinitely without reloading (a provision might easily be added to disable booting from SRAMs and revert to on-motherboiar EPROMs if battery power is lost). If SRAMs are used, the design would be compleely free of any programmed chips.
The design was developed on a 160x100mm single-sided prototype PCB with 0.1 inch dot raster. All chips are socketed for easier experimenting, and connected by soldering 0.25mm wire-wrap wire, except for ground and Vcc which use much thicker wires. Board sits in the 64-pin "megabus" expansion port of my MegaST; this port is logically equivalent, as far as this application is concerned, to connecting it directly to the CPU bus, for example in a chip-socket soldered piggyback upon the CPU. Beside this connector, only the power supply (5V) is needed, and two additional connections on the motherboard. These connections are made at or near W2 jumper on the motherboard which is used to select ROM configuration. The computer can be completely reverted to original state by removing the board and putting the W2 jumper back in place.
The board contains a total of 15 logic chips. Address range and CAS is decoded by a 74HCT138 chip, and addresses are multiplexed by three 74HCT157 chips. DTACK is produced by an open-collector 74LS09. Unused gates from this chip were used to improve the recovery time of the RAS and CAS signals at the end of acccess cycle. RAS/CAS delay sequence is produced by a series of Schmitt triggers in a 74LS14 chip. Interface beween the DRAMs and the computer data bus is by a pair of 74F245 bus transcievers. Multiplexed addresses are fed to the DRAMs through 74F244 and 74F125 bus buffers, which was an addition to the original design because the 74HCT157 address-multiplexers turned unable to drive the full load of 8 SIMMs (in retrospective, my decision to use 1MB modules was probably a bad idea; using an 8MB/72-pin module the load would probably be lower sufficiently that the two bus-buffer chips could be omitted; using a 16MB module would probably have simplified the design further by one or two chips because of the smaller number of CAS lines). Btw. someone with access to more exotic 74** chips like the 74F711-1 containing a five-fold 2:1 multiplexer with bus-driving outputs and integrated 30-ohm resistors (instead of the 74HCT157, 74F244 and 74F125), might further reduce the chip count by about three.
CAS-before-RAS DRAM refresh is used, i.e. with the internal row-counters in the DRAM chips. CAS-RAS refresh sequence is initiated whenever a memory access outside of the Alt-RAM memory area is attempted (i.e. any access to ST-RAM, I/O area or ROM initiates a refresh). Even if the computer is just sitting, displaying a desktop, hblank (hsync) routines (i.e. access to ROM or ST-RAM) execute sufficiently often to perform a refresh. A slight drawback of this concept is that the OS (or, more accurately- the hblank routines) can not be located in Alt-RAM, but having the two systems in on-board EPROMs, and with a possibility to replace these EPROMs with static RAMs into which the OS can be loaded, I do not consider this a serious obstacle. On the other hand, as the refresh is performed only when a memory access elsewhere is in progress, there are never any wait cycles. As a result, all programs run 3-5% faster from this Alt-RAM than previously from ST-RAM.
The board with a complete 8MB load and two EPROMs draws about 700mA. My MegaST-4 draws, when the floppy drive is working, about 2100mA. With the Alt-RAM board added, and with the FPU-board (200mA) which I added earlier, this adds-up to a requirement for current of 3000mA, i.e. exactly the declared capacity of the Mega's power supply. I did not like this, so I replaced the power supply with another one which I had (4A/5V; 1.6A/12V). I suppose that, had I used one 8MB memory module instead of eight 1MB modules, the power required would be significantly less so that possibly the original power supply could be kept.
In order to take care of the increased heating, I installed an additional fan into the Mega's box, in the corner diagonally opposed to the location of the poser supply. This fan pushes new air in, to the nearby Alt-RAM board and the CPU, while the power supply fan pushes the heated air out in the opposite corner.
The board works fine on a 8MHz MegaST, and the timings would be ok for a 10MHz or (somewhat marginal) for 12MHz acceleration, but most probably would -not- work for 16MHz access without some changes.
A small program (thanks to everyone who helped me with this) is used at boot time to declare Alt-RAM to the system. The program reads Alt-RAM configuration (size and starting address) from a small config. file.
Some problems were encountered during development. Slight low-pass filtering of the AS signal was required. I found out that 74F245 chips of different manufacturers behave noticeably differently regarding logic levels and delay times. Then, I had the bad luck that the set of 1MB SIMMs I obtained some long time ago were for 3.3V, which, of course, I did not know and which produced a lot of errors until I discovered the cause. It turned out that 1MB SIMMs, while not costing anything, are not easyto find anymore, so I provided the 3.3V and, after some experimenting, convinced the SIMMs to work. Another problem occured with the DMA-chip (see my other post). A long time ago, in this computer the two ROM chips were replaced by six EPROMs with TOS1.4. Later, I added a FPU board. Addition of this Alt-RAM board seems to have been too much on the data bus for the poor DMA chip which obviously does not have enough bus-driving power and started producing data errors (btw. this is the CO25913-38 chip which was reported to produce disk errors in STe computers). I found out that by removing either the new TOS 2.06 EPROMs or any two (out of six) of the old TOS 1.4 EPROMs, the errors disappear. As I do not like the idea of replacing the DMA chip (not socketed, and, besides, I do not have another one), I have yet to decide what to do: completely remove old TOS 1.4 or remove the new EPROMs and load TOS 2.06 into ST-RAM using the old TOS 1.4. Or else- I may consider changing the design of the board so that the new EPROMs sit "behind" the Alt-RAM bus transcievers and do not additionally load the data bus. But this may require one chip more on the board.
The board is currently in my Mega (less the EPROMs for the moment) with full 8MB Alt-RAM, and the just-noticeably increased speed, together with larger memory (more then 10MB free with NVDI, some accessories and other things loaded) and ability to load items previously impossible, gives a very nice feel. OS replacements/expansions like Magic or Mint or a nice desktop like Jinnee become realistic options instead of hypothetical possibilities.
Recently I have made an upgrade for my MegaST (see my other post), the upgrade consisting of 8MB of Alt-RAM and EPROMs for TOS 2.06. TOS 2.06 can be switched off and the machine reverted to on-motherboard TOS 1.4.
In testing the card, I noticed that errors in hard disk access happen. I found out that errors disappear if I remove the TOS 2.06 EPROMs, but occur again if those are physically in the machine, even if they are deactivated and the computer is running old TOS 1.4. Then I found out that the errors disappear again if I remove just any two or four of the six old TOS 1.4 EPROMs and boot the computer from new TOS 2.06 EPROMs.
Further tests showed that the frequency of disk errors was significantly reduced (but not completely eliminated) if I placed a very large (several uF) decoupling capacitor immediately next to DMA chip, and reduced even more if power supply voltage was increased to cca 5.10 V.
Checking the part number of the DMA chip, I found out that it was the CO25913-38, which was reported to produce exactly this type of errors in some STEs (and MegaSTEs?).
My conclusion is that the CO25913-38 version of DMA chip simply does not have enough bus-driving capacity and is thus producing erroneous data on the bus. It seems that it was running near its limits from the start, so that in the original state of my MegaST this made no problems, but since then the data bus in this computer has been loaded more and more with:
- replacing the original two ROM chips with six-chip TOS 1.4;
- adding the FPU;
- adding the TOS 2.06 EPROMs;
- adding the bus transcievers for Alt-RAM;
which, apparently, was just too much for the DMA chip. I suspect that a STe, having a different hardware design than a ST, presents an even higher bus load which he CO25913-38 chip can not handle.
So, beside the STe owners, anyone attempting adding upgrades which sit on the data bus in a ST-series computer should beware of this version of the DMA chip.