Newsdee wrote:I suspect there is an intention to do more than a SNES core. It might not be released publicly but if they open up an API to develop for it, that would be interesting for open source cores.
Locutus73 wrote:Just a flight of fancy: I know that we are just staring at a picture, but is it conceivable to suppose a methodology in order to jailbreak and port MiSTer to this platform? Is there anything in this picture that automatically excludes this hypothesis?
Kevtris jailbreaked the NT Mini in the past, but noting is sure about this new platform; anyway Kevtris jaylbreak would be closed source. Imagine instead a Super NT booting MiSTer and with a special core that loads standard firmware.
Would be anyone (I know, I know, nowadays anyone=Sorgelig) interested exploring this scenario, if necessary with a fundraised Super NT?
Newsdee wrote:I don't think it makes a lot of sense to port cores to it, at least right now. There are more MISTs in the wild and MiSTer is completely open running on easily available boards with much more resources (the Super NT has about 40KLE)
Newsdee wrote:Plus there is no way to plug a keyboard, so only console amd arcade cores would be a good fit.
Newsdee wrote:Personally I'd rather see improvements to those open cores than ports to new hardware
Sorgelig wrote:Porting the MiST probably possible, but not MiSTer. MiSTer already depends on HPS,
Sorgelig wrote:so it will be hard to put the ARM code back to MCU preserving the current features.
Sorgelig wrote:The size of FPGA is also close to MiST size. Since you have to use HDMI Scaler IPs, the usable size of FPGA for cores will be pretty close to MiST size.
Locutus73 wrote:Isn’t Super NT based on Altera Cyclone V as MiSTer’s Terasic DE10-nano?
Locutus73 wrote:I’m lost here. Can you help me to understand?
Locutus73 wrote:So DE10-nano has a discrete scaler?
Sorgelig wrote:Cyclone V FPGAs have 2 major groups with 3 sub-groups in each. And each sub-group has up to 5 FPGA sizes.
Cyclone V is too generic name to judge the compatibility.
Super Nt uses Cyclone V E with 18.5K ALM FPGA-only
DE10-nano uses Cyclone V SE with 41.5K ALM FPGA with HPS.
Sorgelig wrote:not sure what i need to explain.[...]so whole FPGA can be used for retro core.
Sorgelig wrote:According to what i found, Mini Nt uses original old-school chips, not FPGA.
Frederir wrote:What about https://github.com/marqs85/ossc ? Would it be possible to use it to replace VIP IP from Altera ?
Sorgelig wrote: Many retro systems didn't follow official standards and had slightly out of standard deviations, but many modern HDMI TVs don't tolerate these deviations.
Sorgelig wrote:Frederir wrote:What about https://github.com/marqs85/ossc ? Would it be possible to use it to replace VIP IP from Altera ?
nope.. it's most useless device i ever bought It's not even scaler. It's simple line doubler/tripler. It has no frame buffer, so it cannot convert the frame rate. Many retro systems didn't follow official standards and had slightly out of standard deviations, but many modern HDMI TVs don't tolerate these deviations.
Scandoubler inside almost every MiST core does the same and doesn't occupy noticeable resources.
Locutus73 wrote:It is my understanding that being a simple line doubler and not being a scaler is an intended “feature”. I think that OSSC is a vertical product engineered in order to have the specific task to reduce the lag at the minimum possible achievable level, so any framebuffer is an unwanted feature. I think XRGB has a framebuffer/scaler, but some enthusiasts don’t want the consequent lag, so OSSC is designed to cover this very specific need.
OK, I know, any framebuffer/scaler could be an optional switchable feature, making it a superior and more flexible product and I agree… but we have to consider that these products cover superfluous needs of enthusiast hobbyists in search of subjective perfection, so cost may not be an issue; one could associate OSSC to an external scaler/video-processor, like a DVDO mini.
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