SDRAM vs DDR technical differences?

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SDRAM vs DDR technical differences?

Postby peepsalot » Wed Jan 01, 2020 7:16 pm

Hello, I'm new to the MiSTer scene and just curious about technical reasons why the separate SDRAM module is needed by many cores. I apologize in advance if its been discussed before, but I couldn't find a detailed description in my searching.
I've already ordered some SDRAM, so I'm not trying to be cheap or whatever, just wondering why the onboard RAM is not viable in so many situations.

I admit I don't understand the fundamental differences in signals/interface between SDRAM vs DDR, but I'm interested in learning. Is it just something like external SDRAM clock can be controlled more precisely/directly? Does the onboard DDR access have to go through ARM cores or something?

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Re: SDRAM vs DDR technical differences?

Postby alexh » Thu Jan 02, 2020 6:52 am

It's all about clock speed and latency. As DRAM evolved to give higher bandwidth the latency (time between request and returned data) got longer due to many factors. But the original systems sometimes rely on exact RAM timing. This can be mimicked using later DRAM by running it many times faster than the underlying core. As the systems being turned into cores become more modern their clock rates get too fast to do this. So the FPGA developers first added caches within the FPGA to reduce calls to DRAM and reduce overall latency but cache misses can't always be hidden and caches reduce the amount of internal FPGA RAM available for cores and eventually someone added an SDRAM module. The ultimate would be an SRAM module but they are very expensive for large capacities. SDR SDRAM is the best compromise between latency, clock rate, bandwidth and price.

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Re: SDRAM vs DDR technical differences?

Postby peepsalot » Fri Jan 03, 2020 8:47 pm

Thanks for the reply.

Is there any specific data on the latency of the DDR3 from FPGA? How far off is it from what's required in the worst case?

I have been downloading and skimming through various DE10-nano resources and I did see that the DDR3 is connected directly to the "HPS" ARM cores, but there's some "FPGA bridge" that can be used to access HPS peripherals from FPGA. I didn't see any details about what this "bridge" even is or how it works though.
Is the latency much worse due to going through ARM interface, or is it more of inherent to the DDR3 chips themselves.

I'm still curious if there's possibly any other, not yet explored tricks to improve DDR3 latency from FPGA side.

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Re: SDRAM vs DDR technical differences?

Postby Sorgelig » Fri Jan 03, 2020 9:16 pm

peepsalot wrote:How far off is it from what's required in the worst case?

It doesn't matter how far. Latency is higher than required for any core to be cycle accurate. It's very fast using burst transfer, but there is no fixed timings for random single word access. DDR3 is shared with ARM CPU and also with scaler.
Some cores don't need to be very cycle accurate, so they can use DDR3. Cores may use DDR3 as a non-RAM (from emulated system view) storage.

As for bridges and peripheral description i believe CD which you can download from Terasic contains such documentation in FPGA folder.

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Re: SDRAM vs DDR technical differences?

Postby overclocked » Sat Jan 04, 2020 7:32 pm

I too are interested in this matter. If compared to memory on Graphics cards today (GDDR5??) are those low latency?

I have this crazy idea about a smart reconfigurable/cache (smaller M10K/BRAM-based) that could be used to alleviate those problems??
Maybe not worth but fun like a mind problem. I don't think I know even close enough about DDR-RAM to be able to pull that off..

Each core/game would maybe have its own Cache rules in setup file, depending on how the pattern they access memory. Start with the basic one for the system and then make it possible to tweek depending on result. Maybe even Live configurable using OSD-menu..

What is the fastest memory access that MISTer needs to handle/emulate?

There must be a way to use this "fast"/ high latency memory in a good way. Thus for the "real" MISTer platform (DE-10 Nano) that 1GB memory is connected to ARM/HPS subsystem isn't it? Thus making it harder. On the SOCkit, both the FPGA AND ARM have a 1GB each separetely which maybe makes it more viable on this less-used platform.

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Re: SDRAM vs DDR technical differences?

Postby Sorgelig » Sat Jan 04, 2020 11:56 pm

It's already done by freezing the emulated system till missing data in cache got filled. Then fast rewind to catch up the passed cycles. This is how soft emulators work. RPi then is your friend. Nothing to do with FPGA in this area.


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