peepsalot wrote:How far off is it from what's required in the worst case?
It doesn't matter how far. Latency is higher than required for any core to be cycle accurate. It's very fast using burst transfer, but there is no fixed timings for random single word access. DDR3 is shared with ARM CPU and also with scaler.
Some cores don't need to be very cycle accurate, so they can use DDR3. Cores may use DDR3 as a non-RAM (from emulated system view) storage.
As for bridges and peripheral description i believe CD which you can download from Terasic contains such documentation in FPGA folder.