SNES core

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Sorgelig
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Re: SNES core

Postby Sorgelig » Thu Jul 04, 2019 9:31 am

SaschaFFM wrote:I wanted to check out on the Cheat-Feature of MiSTer. It appears that the site https://gamehacking.org which is linked in the MiSTer-Github as a resource has been without any content (blank page) for a couple of weeks now.

Does anybody have a link to a collection of Cheats especially for SNES and Genesis? That would be great!


It's probably because you disable scripts in your browser. For me site is working fine.
Updater script downloads all cheats as far as i know.

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Re: SNES core

Postby paulbnl » Thu Jul 04, 2019 11:01 am

There seems to be some IP address blocking going on at gamehacking.org. I am also getting empty pages (0 byte content) but it works with a VPN.

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Re: SNES core

Postby PhantombrainM » Thu Jul 04, 2019 4:14 pm

Okay. That's true. Havent received cheats for over a month but thought there were no new one's.

Checked the website above and its only blank and white in Germany.
Connected to Switzerland, still empty. Connected to the United states and it shows up now...
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Re: SNES core

Postby guvner » Thu Jul 04, 2019 4:43 pm

the past two official builds give me garbled screens and/or black screen after the intro logo when loading games. I just compiled a build with quartus 17.1 and that doesn't exhibit any of those problems.

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Re: SNES core

Postby srg320 » Fri Jul 05, 2019 8:04 am

dentnz wrote:Hi srg320,

I have started to look at implementing MSU-1 support to your SNES core:
http://helmet.kafuka.org/msu1.htm

So far I have setup some code in verilator (SystemVerilog), and begun adding functionality to handle the MSU_ID, MSU_STATUS and MSU_TRACK registers for both read and write. I have also started to add the code into a fork or your repository (I will make this public soon). I thought I would reach out to you now to ask a few questions before I proceed much further:

1) Are you planning or are currently working on MSU-1 support? If so, I can help, or leave you to it! :) Up to you!
2) If I was to add in support, I notice you have a src/chip folder containing the additional special chip implementations, along with a mapper pattern to select these chips onto the bus... I have created another chip folder (src/chip/MSU) and started to add a MSU map. Would this be your preferred method for adding in MSU functionality? Even considering it is not a real special chip?
3) Are you okay with me adding further SV to your project? Given that the majority of your code is VHDL?

Cheers,
dentnz

Hi dentnz,

1) I don't plan on making a MSU-1.
2) It doesn't matter.
3) It doesn't matter.

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alexh
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Re: SNES core

Postby alexh » Fri Jul 05, 2019 3:10 pm

Slightly off topic but if anyone needs to convert VHDL -> Verilog (2001, 2009 or SystemVerilog) I worked on an automated tool to do it which uses Formality to prove it is logically identical to the VHDL. In 2001 mode it struggles with advanced use of records, particularly multidimensional arrays of them as ports but in SV mode it can handle pretty much anything. If you want something converted (Single language simulations are much faster than mixed mode) then send me a PM and I should be able to return it same day.

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Re: SNES core

Postby trashuncle » Fri Jul 05, 2019 9:39 pm

guvner wrote:the past two official builds give me garbled screens and/or black screen after the intro logo when loading games. I just compiled a build with quartus 17.1 and that doesn't exhibit any of those problems.


I had the same issue until I turned off Low Latency mode. Not sure why, but it seemed to help. I think there may be something wrong with the current complied build.

Sorgelig
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Re: SNES core

Postby Sorgelig » Sat Jul 06, 2019 9:23 am

alexh wrote:Slightly off topic but if anyone needs to convert VHDL -> Verilog (2001, 2009 or SystemVerilog) I worked on an automated tool to do it which uses Formality to prove it is logically identical to the VHDL. In 2001 mode it struggles with advanced use of records, particularly multidimensional arrays of them as ports but in SV mode it can handle pretty much anything. If you want something converted (Single language simulations are much faster than mixed mode) then send me a PM and I should be able to return it same day.

I'm not interesting in asking for conversion, but if you will release your tool, then i would like to use it.

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Re: SNES core

Postby kitrinx » Sat Jul 06, 2019 1:20 pm

alexh wrote:Slightly off topic but if anyone needs to convert VHDL -> Verilog (2001, 2009 or SystemVerilog) I worked on an automated tool to do it which uses Formality to prove it is logically identical to the VHDL. In 2001 mode it struggles with advanced use of records, particularly multidimensional arrays of them as ports but in SV mode it can handle pretty much anything. If you want something converted (Single language simulations are much faster than mixed mode) then send me a PM and I should be able to return it same day.


I would also be interested in using that if you ever make it available for the use of others. I would love to convert some NES code to verilog so I could use it in verilator.

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alexh
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Re: SNES core

Postby alexh » Sun Jul 07, 2019 1:43 pm

I can't release my tools. All my work is owned by my employer Toshiba. And it currently uses Synopsis Formality as the backend (although I'm looking into the free tool SymbiYosis) and licences cost $10000+. Point me to the VHDL and I'll convert the files. Depending on how many files and the complexity of the VHDL configuration file and the number/size of generics/parameters it will only take a few minutes.

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kitrinx
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Re: SNES core

Postby kitrinx » Sun Jul 07, 2019 4:12 pm

alexh wrote:I can't release my tools. All my work is owned by my employer Toshiba. And it currently uses Synopsis Formality as the backend (although I'm looking into the free tool SymbiYosis) and licences cost $10000+. Point me to the VHDL and I'll convert the files. Depending on how many files and the complexity of the VHDL configuration file and the number/size of generics/parameters it will only take a few minutes.


For NES, the T65 CPU: https://github.com/MiSTer-devel/NES_MiS ... master/t65

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Re: SNES core

Postby rezb1t » Sun Jul 07, 2019 4:42 pm

alexh wrote:I can't release my tools. All my work is owned by my employer Toshiba. And it currently uses Synopsis Formality as the backend (although I'm looking into the free tool SymbiYosis) and licences cost $10000+. Point me to the VHDL and I'll convert the files. Depending on how many files and the complexity of the VHDL configuration file and the number/size of generics/parameters it will only take a few minutes.

If you could convert the MSX core, I would appreciate it.

https://github.com/MiSTer-devel/MSX_MiSTer

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Re: SNES core

Postby cyb4 » Sat Jul 13, 2019 8:41 am

Today, I tried to play Tengai Makyou Zero with the latest English translation patch, but the game doesn't start and the screen stays black. Is this fixable? That would be awesome!

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Re: SNES core

Postby bitfan2011 » Mon Jul 22, 2019 3:42 am

does TG16 core need to be converted to verilog?

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Chol
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Re: SNES core

Postby Chol » Sat Jul 27, 2019 6:43 pm

Another FPGA implementation was released yesterday: https://github.com/pgate1/SNES_on_FPGA

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Re: SNES core

Postby DrOG » Sun Jul 28, 2019 3:39 am

It's language is SFL+ instead of the popular Verilog or VHDL... Is this core better/smaller than the existing one? I suspect the current SNES core available on MiSTer platform is more mature, as it has been polished during months by different persons. If the linked new core is small enough perhaps it's portable to MiST, but I'm not sure, as I'm not an FPGA expert...

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Re: SNES core

Postby Dirtbag » Sun Jul 28, 2019 10:10 am

Looks like Pgate1 ported a WIP version to MiSTer a while ago https://pgate1.at-ninja.jp/SNES_on_FPGA/ it's towards the bottom of the page. Also they have a SPC player that looks cool.

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Re: SNES core

Postby Piacenti » Sun Aug 04, 2019 10:55 pm

What’s the best settings in mister.ini to reduce lag from HDMI? I’m using vsync_adjust 2, can I do something more?

Sorgelig
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Re: SNES core

Postby Sorgelig » Mon Aug 05, 2019 3:05 pm

vsync_adjust=2 already eliminates HDMI lag on MiSTer side.

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Re: SNES core

Postby Lightwave » Mon Aug 05, 2019 5:09 pm

Piacenti wrote:What’s the best settings in mister.ini to reduce lag from HDMI? I’m using vsync_adjust 2, can I do something more?


The other related setting would be setting the video mode to the native resolution of your HDMI display, removing the need for any additional scaling (possibly improving display latency)


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