Jaguar

https://github.com/MiSTer-devel/Main_MiSTer/wiki

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Frederir
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Jaguar

Postby Frederir » Sun Apr 29, 2018 9:46 am

Would mister be big enough to fit the jaguar design :
https://github.com/Torlus/JagNetlists

Which is interesting because it is translated from the original netlist :
https://github.com/Torlus/JagNetlists/t ... tlists_org
With both Tom and Jerry chip.

The design fit in a Stratix II : EP2S60F672C3

F.

Sorgelig
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Re: Jaguar

Postby Sorgelig » Sun Apr 29, 2018 2:37 pm

by raw specs MiSTer's FPGA is bigger, so most likely it will fit.
As far as i know this core is in POC state. Even with small cores there is a big distance between getting "hello world" and usable state.
To make this core work in the way other cores are working, the developer has to know the Jaguar architecture as his fingers.

Anyone is welcome to try to port and finish this core :)

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alexh
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Re: Jaguar

Postby alexh » Sun Apr 29, 2018 5:15 pm

The original netlists contained non synthesisable code (after all it was a technology specific netlist). This code has been fixed and made functional?

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Re: Jaguar

Postby Gehstock » Sun Apr 29, 2018 5:28 pm

should be ok

Flow Status Successful - Sun Apr 29 19:16:37 2018
Quartus Prime Version 17.0.2 Build 602 07/19/2017 SJ Standard Edition
Revision Name jag_s2
Top-level Entity Name jag_s2
Family Cyclone V
Device 5CGXFC7C7F23C8
Timing Models Final
Logic utilization (in ALMs) 8,031 / 56,480 ( 14 % )
Total registers 7658
Total pins 59 / 268 ( 22 % )
Total virtual pins 0
Total block memory bits 406,128 / 7,024,640 ( 6 % )
Total DSP Blocks 7 / 156 ( 4 % )
Total HSSI RX PCSs 0 / 6 ( 0 % )
Total HSSI PMA RX Deserializers 0 / 6 ( 0 % )
Total HSSI TX PCSs 0 / 6 ( 0 % )
Total HSSI PMA TX Serializers 0 / 6 ( 0 % )
Total PLLs 1 / 13 ( 8 % )
Total DLLs 0 / 4 ( 0 % )

Sorgelig
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Re: Jaguar

Postby Sorgelig » Sun Apr 29, 2018 8:37 pm

Gehstock wrote:should be ok

Why you test it on CycV GX? Don't you have MiSTer anymore?
8K ALM? It is very low usage considering the whole Jaguar complexity.

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Eero Tamminen
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Re: Jaguar

Postby Eero Tamminen » Sun May 06, 2018 7:58 am

Sorgelig wrote:by raw specs MiSTer's FPGA is bigger, so most likely it will fit.
As far as i know this core is in POC state. Even with small cores there is a big distance between getting "hello world" and usable state.
To make this core work in the way other cores are working, the developer has to know the Jaguar architecture as his fingers.


There are 3 processors in Jaguar and while 68000 runs only at 13.295 MHz, Tom (GPU) & Jerry (DSP) run at 26.59 MHz (according to Wikipedia).

Is MiSTer fast enough to run all of these at required speed?

Sorgelig
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Re: Jaguar

Postby Sorgelig » Sun May 06, 2018 8:34 am

ZX Spectrum runs on up to 56MHz in turbo mode and currently limited by SDRAM speed.
The max clock depends on the code. For well written code it's not a problem to simulate 26.59MHz and even much higher clocks.


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