thanks

Moderators: Mug UK, Zorro 2, Greenious, spiny, Sorgelig, Moderator Team
nightshadowpt wrote:If not, why not?
alfishe wrote:But as for raw performance of FPGA fabric - it's the same, moreover Cyclone V has lower max operational frequencies than Cyclone III.
So Minimig core in current state will be almost the same or slightly slower in performance (slightly above stock A1200 in my case).
alfishe wrote:But as for raw performance of FPGA fabric - it's the same, moreover Cyclone V has lower max operational frequencies than Cyclone III.
So Minimig core in current state will be almost the same or slightly slower in performance (slightly above stock A1200 in my case).
Sorgelig wrote:... Performance of Minimig on MiSTer is exactly the same as on MiST. It has nothing to do with particular FPGA chip.
FPGA is not CPU - it cannot be faster or slower on particular core. This is one of fundamental difference between FPGA and CPU. As long as core compiled successfully - it works exactly the same on Cyclone II, Cyclone III, Cyclone V.
ijor wrote:That's not always true. It is when the clock frequency is fixed at compilation time, the typical case in this type of cores. But it is not always like this. A core might be fed by an external clock, or the frequency of the clock might change at runtime. In those cases a faster FPGA would have a higher max frequency for a given compilation and would allow connecting a clock at a higher frequency.
ijor wrote:I don't think the MiST has a faster FPGA than the MiSTer. It is true that the Cyclone V generation is slightly slower than the Cyclone III one. But the FPGA on the MiST is speedgrade -8 (the slowest), and on the MiSTer is -7 (faster). The speedgrade difference is more significant than the generation performance in most cases.
Sorgelig wrote:There is no point to talk about FPGA usage in other area. Different tasks have different limitations. We are talking about retro emulation. I just tell that clock propagation in FPGA is not like a single wire through whole core. Fitter inserts many fixes of clock propagation delay. Sometimes it adds a delay to skip a whole cycle to meet constraints. If you supply the external clock with different frequency, it will destroy the timings and core will misbehave. While some designs may accept variable clock, it's not a general case. Core is usually compiled for specific clocks.
It's not correct to compare Cyclone III and Cyclone V by just speed grade. Cyclone V has finer process and cell speed is faster, ...
Sorgelig wrote:P.S. Would be better if you would put part of your argue effort to core developing. That would be more helpful.
nightshadowpt wrote:From your explanations, I understand that using the current (low cost) FPGAs, we'll never be able to attain Amiga 4000 speeds, right?
Sorgelig wrote:On high clocks like 50MHz and more it's common thing for compiler to insert delays skipping the whole cycle. Has nothing to do with bad design. Lower clocks usually have no problem but it has no relation to FPGA speed and Fmax.
P.S. Would be better if you would put part of your argue effort to core developing. That would be more helpful.
ijor wrote:That's precisely my point.
ijor wrote:Well, to be honest, I considered porting the ST core, and time permitting, I might still eventually do it. But I am a fan of cycle accuracy.
hansencj wrote:I find the Mister very confusing and non-obvious to setup and get working. I am trying to run the Amiga configuration. How do I setup the Amiga OS to work on the sd card? I managed to get the kickstart rom 1.3 going, but how do I install Workbench 1.3?
Thanks for your help.
hansencj wrote:Can someone just put a complete sd card image up on github? It would seem a lot easier for people trying to get started.
Users browsing this forum: No registered users and 2 guests