Minimig and Hybrid emulation.

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Minimig and Hybrid emulation.

Postby Sorgelig » Sun Nov 26, 2017 2:18 am

I want to bring attention to one interesting thing which can be achieved on MiSTer. It's hybrid emulation. It's where both emulation worlds can meet each other.

It's not a secret that weak part of Minimig is CPU emulation. While it's OK and can match a real A1200 speed and even can be faster, it's always wanted to have something more powerful. And the bottleneck is CPU. Currently only 68000 with some subset of 68020 is available in HDL. The most important parts MMU and FPU are not available and probably won't be available in foreseen future. At the same time soft emulator UAE emulates MMU and FPU very well while chipset features slowing down UAE4ARM very much.

So, here is an idea: Emulate the whole AGA chipset with ChipRAM on FPGA (it's what Minimig does well) and emulate 68030/40/60 with FastRAM on ARM. Hybrid FPGA used in DE10-nano provides high-speed bridges, so from ARM side it will look like a real Amiga 1200 is connected to the ARM.
I've saw screens of SysInfo from some UAE4ARM versions with insanely big numbers. So, i'm sure such hybrid emulator will beat any real 68060 CPU. And most important it's free. No any additional hardware is required.

This is only an idea but it's pretty viable. Need developer(s) who could make it possible. Actually all parts (Minimig, UAE) are already available and open source. Need to do a work to mix them together.

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Re: Minimig and Hybrid emulation.

Postby JimDrew » Tue Nov 28, 2017 8:38 am

As I stated in the DE-10 thread, if someone is willing to setup a developer environment where I can compile ARM assembly, then I will port my x86 assembly 68040 core over to ARM assembly.
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Re: Minimig and Hybrid emulation.

Postby alexh » Tue Nov 28, 2017 12:31 pm

Out of interest what are the signals which would need to go between the ARM and the FPGA?

A good proportion of the signals on an Amiga CPU bus slot I imagine? 24-bit address, 32-bit data, read/write/address strobes, irqs etc. perhaps 100 signals?

Presumably you'd have to multiplex the signals at a higher clock rate to get them through as there are unlikely to be enough I/O?

Or perhaps use a GIGABIT SERDES with a parallel data wrapper (In Xilinx these are known as Aurora) if the Cyclone V has them?

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Re: Minimig and Hybrid emulation.

Postby Sorgelig » Tue Nov 28, 2017 2:00 pm

This is easiest part - there is 128bit HPS-FPGA bridge: 128bit data (separate 128bit for read and 128bit for write) and 32bit address. I think it's even too much, and lightweight HPS-FPGA bridge which provides 32bit data should cover all needs. Minimig, actually uses 16bit data bus, not 32bit.

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Re: Minimig and Hybrid emulation.

Postby fpgaarcade » Tue Nov 28, 2017 3:40 pm

I've been looking at the same thing, although with a PI CM3 compute module.

http://www.fpgaarcade.com/punbb/viewtopic.php?id=1221

You have tighter integration with the FPGA. I'm having to use the SMI, but the "fast" memory and RTG is essentially in the CM3. The CPU stalls in a similar fashion to a real plug in card when accessing the Amiga hardware.

I've stalled the project while I do Replay2. I decided not to use the embedded CPUs in the ZYNQ etc as the PI offers more performance for much less cost.
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Re: Minimig and Hybrid emulation.

Postby Sorgelig » Tue Nov 28, 2017 4:14 pm

fpgaarcade wrote:I decided not to use the embedded CPUs in the ZYNQ etc as the PI offers more performance for much less cost.

DE10-nano already has internal ARM. So, for MiSTer project it's cheaper than any add-on, because it's free.
Currently only one core of ARM is used for Linux. Another core is completely free and can be used solely for 680x0 emulation.

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Re: Minimig and Hybrid emulation.

Postby stimpy » Tue Nov 28, 2017 7:48 pm

Out of interest, why not just use the arm to run an emulator? The emulators are cycle accurate are they not?
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Re: Minimig and Hybrid emulation.

Postby Newsdee » Tue Nov 28, 2017 10:42 pm

stimpy wrote:Out of interest, why not just use the arm to run an emulator? The emulators are cycle accurate are they not?

It's because it requires much more power to do full emulation from a CPU like an ARM chip. A CPU can only do one task at a time and in order to be cycle accurate it has to process things very quickly to be ready on time (otherwise there's lag or glitches). Which is why Higan/BSnes needs a 3Ghz+ CPU to accurately emulate the SNES.

With FPGAs (and ASICs) the difference is the chip can process everyhing truly in parallel. Assuming you have access to the same kind of RAM, they can act exactly like the real thing. Boards like the MiST and MiSTer are somewhere in between whereby some non time-critical operations are offloaded to the ARM CPU (e.g. file I/O), with the rest of the machine running in FPGA.

What's being discussed here is to emulate the CPU with the ARM while leaving everything else on the FPGA side. Fact is we have a 800Mhz CPU on the MiSTer and it's under utilized right now. It should, a priori, give much better performance than a RPi Amiga emulator running fully on CPU. It also helps reduce some development time since it allows to reuse CPU code (instead of porting it to the FPGA). At the very least it's an interesting and exciting approach. :)

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Re: Minimig and Hybrid emulation.

Postby Newsdee » Tue Nov 28, 2017 11:01 pm

Here's an interesting discussion on input lag and a method to test for it:
https://forums.libretro.com/t/an-input- ... ation/4407

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Re: Minimig and Hybrid emulation.

Postby Sorgelig » Tue Nov 28, 2017 11:53 pm

stimpy wrote:Out of interest, why not just use the arm to run an emulator? The emulators are cycle accurate are they not?

As Newsdee mentioned already, emulating a complex Amiga chipset requires a lot of CPU power when it emulates on ARM. RPi2 fails to keep up the Amiga 500 speed on such apps like Spaceballs demo. You will see freezes while watching this demo.

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Re: Minimig and Hybrid emulation.

Postby stimpy » Wed Nov 29, 2017 1:59 pm

I'm well aware the diferences between FPGAS and prcoessors :o I see now that the emulators are not as good as I assumed, I thought that would be sorted considering we are +30 years on the tech...
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Re: Minimig and Hybrid emulation.

Postby kolla » Thu Nov 30, 2017 8:58 am

I wonder which approach is best... adding an emulated CPU from UAE to the existing Minimig core, or adding FPGA enhanced chipset from Minimig to UAE :)

There are certain features of UAE that I think would be great to have even as FPGA is used for chipset.
* various uae-resources, disk I/O, accessing host file system
* built in TCP/IP using bsdsocket.library from UAE
* emulation of various I/O hardware (for example A2065)
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Re: Minimig and Hybrid emulation.

Postby kolla » Thu Nov 30, 2017 9:13 am

Btw - I am not quite sure, but I think potentially the FleaFPGA "Ohm" can be strapped on top of a Raspberry Pi, and may also be a possible candidate for this kind of hybrid emulation.
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Re: Minimig and Hybrid emulation.

Postby stimpy » Thu Nov 30, 2017 11:08 am

...thinking about this more, if it needs to be a cycle accurate system (where FPGA is king) to run certain games and demos then adding a super fast 68000 will break it in most cases. The MegaSTE could be switched down to 8MHz for this very reason.
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Re: Minimig and Hybrid emulation.

Postby kolla » Thu Nov 30, 2017 3:41 pm

That's the thing - for old games and demos demanding cycle exact CPU and all, stay on FPGA. But for legacy applications (and even many games and definitely demos), cycle exact CPU is a non-issue, faster is better, features like FPU and even MMU are important. The problem with emulation on for example Raspberry Pi (and even modern high-end PCs), is not emulation of CPU, but emulation of the chipset. Some effect that is very lightweight on the Amiga chipset, can still be quite demanding to emulate.
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Re: Minimig and Hybrid emulation.

Postby Sorgelig » Thu Nov 30, 2017 7:27 pm

kolla wrote:The problem with emulation on for example Raspberry Pi (and even modern high-end PCs), is not emulation of CPU, but emulation of the chipset. Some effect that is very lightweight on the Amiga chipset, can still be quite demanding to emulate.

is it something different than i wrote in the first post?

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Re: Minimig and Hybrid emulation.

Postby JimDrew » Thu Nov 30, 2017 8:27 pm

You can write cycle exact emulation with software. If your native CPU is fast enough, you could do it in C (but C is very slow). The most accurate method is to use a timer interrupt to handle the emulated CPU instruction decoding, with the timer's timeout set to the duration of the emulated instruction. ie. emulated instructions that require four 1us cycles need the timeout to be 4us. This is a LOT easier in assembly, where you know the exact number of native instructions that are executing. With C you are at the mercy of the compiler, which are horrible at things like this - and different compiler versions can often times yield different results. This is why I have written all of my emulators in assembly (no matter what CPU they run on). If you don't care about cycle exact, you can run the emulation without using the interrupt to queue the decoding. It's easy enough to make a single program do both.
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Re: Minimig and Hybrid emulation.

Postby Sorgelig » Thu Nov 30, 2017 8:55 pm

Cycle exact is not important for Amiga emulation. Amiga had different CPUs, so most games/demos take it in account. Amiga has other ways to synchronize operations to video, so exact amount of CPU cycles is not important in Amiga case.
More important is feature set of CPU like MMU, FPU.

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Re: Minimig and Hybrid emulation.

Postby kolla » Fri Dec 01, 2017 8:04 am

Sorgelig wrote:is it something different than i wrote in the first post?


Nope, just repeating the gospel :)
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Re: Minimig and Hybrid emulation.

Postby JimDrew » Fri Dec 01, 2017 3:36 pm

Sorgelig wrote:More important is feature set of CPU like MMU, FPU.


I agree, which is why FUSION-PC (Mac emulation on PC hardware) emulated the MMU and FPU.
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Re: Minimig and Hybrid emulation.

Postby stimpy » Thu Dec 07, 2017 3:00 pm

Had another thought on this. If the processor was emulated on the ARM would the RAM also need to be on the ARM side to achieve the expected speed?
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Re: Minimig and Hybrid emulation.

Postby alfishe » Thu Dec 07, 2017 4:19 pm

Sorgelig wrote:I
This is only an idea but it's pretty viable. Need developer(s) who could make it possible. Actually all parts (Minimig, UAE) are already available and open source. Need to do a work to mix them together.


Very interesting idea, although, currently high speed transfers to-from FPGA disabled. Enabling bi-directional transfers is a pre-requisite to start that work. Ideally, if it can be used also for other transactions as well (large file-data blocks transfer, full screen true color OSD).

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Re: Minimig and Hybrid emulation.

Postby Sorgelig » Fri Dec 08, 2017 12:30 am

stimpy wrote:Had another thought on this. If the processor was emulated on the ARM would the RAM also need to be on the ARM side to achieve the expected speed?

As I've wrote it in the first post: CPU+FastRAM should be on ARM side. Since FastRAM is accessible only by CPU, there is no reason to split them to different sizes. ARM has cache which will eliminate a complex interface if FastRAM would be on FPGA side.

alfishe wrote:currently high speed transfers to-from FPGA disabled. Enabling bi-directional transfers is a pre-requisite to start that work.

They are not disabled. They are not used.

alfishe wrote:Ideally, if it can be used also for other transactions as well (large file-data blocks transfer, full screen true color OSD).

You should already start to re-design the code. So, where are you now? ;)


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