MISTer on DE0-nano?

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Re: MISTer on DE0-nano?

Postby ijor » Mon Dec 04, 2017 12:15 pm

olin wrote:- installed sd card with (Main_)MiSTer (latest one from releases directory). Linux booted MiSTer was executed ...


Btw, I wonder if the U-boot and the preloader are fully portable. Obviously it works, and I guess that's because the main boot parameters, the DRAM type and the main clock are identical. But Terasic has at least five of those similar boards. And I wonder why each has a separate build if they all could use the same image.

Sorgelig, have you seen a reference about the portability?

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Re: MISTer on DE0-nano?

Postby Sorgelig » Mon Dec 04, 2017 12:31 pm

ijor wrote:Btw, I wonder if the U-boot and the preloader are fully portable. Obviously it works, and I guess that's because the main boot parameters, the DRAM type and the main clock are identical. But Terasic has at least five of those similar boards. And I wonder why each has a separate build if they all could use the same image.

Sorgelig, have you seen a reference about the portability?

HPS parts in most Cyclone V FPGAs are pretty identical. And if used memory is the same as in DE10-nano (1GB DDR3), then from HPS point of view these systems are identical. So, i don't see anything magical here.
And since all these boards are from Terasic, it's more likely they use the same peripheral chips.
I was confident that Linux part should work on DE0-nano SocKit. It also should work on DE1-SoC and DE10-standard.

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Re: MISTer on DE0-nano?

Postby ijor » Mon Dec 04, 2017 12:54 pm

Sorgelig wrote:And since all these boards are from Terasic, it's more likely they use the same peripheral chips.
I was confident that Linux part should work on DE0-nano SocKit. It also should work on DE1-SoC and DE10-standard.


Yes, it makes sense and that's what I thought. Just wondering why they have separate builds for each board, then. But may be there is no particular reason and it's just because that's the way they use to organize the builds.

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Re: MISTer on DE0-nano?

Postby olin » Mon Dec 04, 2017 10:40 pm

Thank you, that was it! VGA_EN pin (GPIO1-10) needs to be grounded which I didn't do while scoping. Once I've put a jumper between pin 10 and 12 I could scope clean hsync and vsync signals. Then after forcing scan-doubler in the config file the picture appeared. Fantastic! Bellow is the snapshot of my cobbled board (you can spot the green jumper between pin 10 and 12) and monitor pictures, the second screen shows auto-adjusted picture after pressing OSD button.

protboard with menu on: http://mujweb.cz/molej/mister/pic/first_screen.jpg

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Re: MISTer on DE0-nano?

Postby Newsdee » Mon Dec 04, 2017 11:18 pm

Wow, great progress!

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Re: MISTer on DE0-nano?

Postby Sorgelig » Tue Dec 05, 2017 12:06 am

Check if USB works.
Connect the USB keyboard.

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Re: MISTer on DE0-nano?

Postby olin » Tue Dec 05, 2017 12:36 am

USB keyboard works fine when plugged via powered USB hub. I could navigate up/down in the menu (F12 or Esc).
When USB keyboard was plugged in I got this serial log output:

Code: Select all

The file event0 was created.
Close all devices.
Open up to 10 input devices.
has LEDs.
opened /dev/input/event0 (258a:0001)
opened /dev/input/event1 (258a:0001)
The file event1 was created.
The directory by-id was created.
The directory by-path was created.
Close all devices.
Open up to 10 input devices.
has LEDs.
opened /dev/input/event0 (258a:0001)
opened /dev/input/event1 (258a:0001)


So USB keyboard hot-plugging works nicely as well.

So far everything works *exactly* as you described in the second post of this thread. :)

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Re: MISTer on DE0-nano?

Postby Newsdee » Tue Dec 05, 2017 1:15 am

Would this use the same SDRAM board as the DE10?

If so, It means they could maybe be made in higher volumes as it's the biggest piece needed by cores. I also guess the VGA could be made as a cheaper cable for the DE0 to reduce costs / complexity for DYI?

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Re: MISTer on DE0-nano?

Postby Sorgelig » Tue Dec 05, 2017 3:12 am

Newsdee wrote:Would this use the same SDRAM board as the DE10?

My SDRAM module should be fully compatible. Arduino socket is shifted by 0.12mm on DE0 which should be no problem to insert.

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Re: MISTer on DE0-nano?

Postby olin » Tue Dec 05, 2017 9:13 am

Newsdee wrote: I also guess the VGA could be made as a cheaper cable for the DE0 to reduce costs / complexity for DYI?


Yes and no. VGA needs at least 14 resistors (12 color + 2 sync) to produce RGB444 colors (to fit Amiga OCS color range). The 'cable' would have to have those resistors embedded somewhere (presumably close to the VGA connector), and the cable would have to have 15 wires (14 + ground) which would make it quite thick. Or you could put the resistors close to the pin header of the cable (to reduce the number of wires to minimum of 6), in that case you'd have to produce some small IO board anyway. Also don't forget the audio out, which needs few more passives. But I get what you mean - to have 'something' that's super easy to solder for beginners (so it doesn't scare them off) and also cheap. The IO board for DE0-nano-Soc can be redesigned to have just RGB444 VGA out and the audio out (no buttons, no external sdcard connector, no pin headers for external buttons or LEDs) and made for through hole components - if that's what DIY beginner would consider to solder.


Sorgelig wrote: Arduino socket is shifted by 0.12mm on DE0


Thanks for the reminder I'll have to adjust the holes on my board layout.

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Re: MISTer on DE0-nano?

Postby Newsdee » Tue Dec 05, 2017 9:36 am

olin wrote:But I get what you mean - to have 'something' that's super easy to solder for beginners (so it doesn't scare them off) and also cheap. The IO board for DE0-nano-Soc can be redesigned to have just RGB444 VGA out and the audio out (no buttons, no external sdcard connector, no pin headers for external buttons or LEDs) and made for through hole components

Exactly, What I had in mind is that the DE0 could reuse the same SDRAM board as the DE10 (so each production benefits both users) and for the other boards maybe have a version that is super easy to solder (e.g. using the big chunky resistors instead of SMD). I guess one could theoretically also make a "chunky" SDRAM board but no idea if parts exist or the resulting speed for it.

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Re: MISTer on DE0-nano?

Postby Sorgelig » Tue Dec 05, 2017 9:41 am

olin wrote:Thanks for the reminder I'll have to adjust the holes on my board layout.

you can consider to use my SDRAM board. It can be mounted horizontally inward. You can cut out the SDRAM board space from your I/O board.
In this case, the same SDRAM board can be used in both DE10-nano and DE0-nano-SoC. It's convenient when you want some one to build the same construction. Those who solder the SDRAM board and sell to others will be able to sell it to DE0 owners.

Not everyone can solder by himself. Especially 54pin chip.

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Re: MISTer on DE0-nano?

Postby olin » Tue Dec 05, 2017 7:35 pm

Absolutely, nothing against it. For me it made sense to initially design and produce just one board instead of two (less expensive). Considering IO board on DE10-nano is optional, it is natural the SDRAM board is separated. On the other hand IO board is required on DE0-nano-soc so both IO board and SDRAM board are needed. If it won't make a technical issue (heat, SDRAM speed, soldering complexity) I might stick to the unified single board design.

I expect there will be few more iterations of the de0-nano-soc IO board before it settles down into something acceptable. In the end it may prove the SDRAM board is better separated, in that case I'll just remove the SDRAM part from the board layout (should be fairly simple) and ensure your universal SDRAM board fits nicely. The IO board design I've made so far is open source (and already published), the editor software is free as well so there is no obstacle for anybody to make changes and improvements. :)

Who knows, maybe the DE0-nano-soc was not so popular after all, so the interest to run MiSTer on it might be quite low anyway...
BTW. my boards were manufactured and are already in the country (according to the tracking service), so expecting delivery soon.

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Re: MISTer on DE0-nano?

Postby ijor » Wed Dec 06, 2017 12:45 am

I just noted that the DE0 has a different FPGA grade than the DE10. The FPGA on the DE10 is I7, on the DE0 is C6.

C type FPGA has a smaller temperature range. That means that if the DE0 has the same heating problems as the DE10 (btw, would be interested to know), then cooling might be more critical.

OTOH, it is a faster speed grade, and among other things you should be able to run the ao486 core better and at a higher frequency. And perhaps even more important, DRAM should work better and some boards that fail on the DE10 might work on the DE0.

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Re: MISTer on DE0-nano?

Postby olin » Wed Dec 06, 2017 1:01 am

ijor wrote: That means that if the DE0 has the same heating problems as the DE10 (btw, would be interested to know), then cooling might be more critical.

Correct. I've compiled ZX-Spectrum core and run it on the DE0-nano-SOC board (no luck running any software on it as I probably don't have the right format of the spectrum rom) , then after some time (~40 minutes) it overheated and produced visual artefacts, menu started to misbehave. I turned it off and let it to cool, after that the DE0 board was OK again. I also compiled TurboGrafx16, but was not able to display the video as the scandobuler doesn't seem to be implemented there yet.

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Re: MISTer on DE0-nano?

Postby Sorgelig » Wed Dec 06, 2017 2:04 am

ijor wrote:That means that if the DE0 has the same heating problems as the DE10 (btw, would be interested to know)

It will produce around the same amount of heat because the source of heat is HPS part (ARM) which is exactly the same on both chips.

ijor wrote:among other things you should be able to run the ao486 core better and at a higher frequency.

not at all. FPGA on DE0-nano-SoC has almost 3 times less ALM than on DE10-nano. ao486 won't fit.

ijor wrote:DRAM should work better and some boards that fail on the DE10 might work on the DE0.

Less likely. The main problem with SDRAM boards are electrical characteristics of GPIO. It has no relation to FPGA speed grade. Although different GPIO traces routing may affect SDRAM board compatibility. It may be worse or better - need to test.

olin wrote:Correct. I've compiled ZX-Spectrum core and run it on the DE0-nano-SOC board (no luck running any software on it as I probably don't have the right format of the spectrum rom)

1) ZX core doesn't require the rom file to run. ROM is integrated into core. External ROM is optional.
2) Last versions of ZX core require SDRAM board.

olin wrote: I also compiled TurboGrafx16, but was not able to display the video as the scandobuler doesn't seem to be implemented there yet.

Many cores don't have (and most likely won't have) scandoubler since VGA output is optional. HDMI has scaler which works better with original video than scandoubled.

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Re: MISTer on DE0-nano?

Postby ijor » Wed Dec 06, 2017 3:35 am

Sorgelig wrote:It will produce around the same amount of heat because the source of heat is HPS part (ARM) which is exactly the same on both chips.


I know, but I think we agreed that, at least partially, the heating is a consequence of the proximity of other components. Anyway, my point is that even if producing exactly the same heat, it is worse for the DE0 since the FPGA is not an industrial grade part and has a smaller temperature operating range.

not at all. FPGA on DE0-nano-SoC has almost 3 times less ALM than on DE10-nano. ao486 won't fit.


Right. Forgot about that.

ijor wrote:DRAM should work better and some boards that fail on the DE10 might work on the DE0.

Less likely. The main problem with SDRAM boards are electrical characteristics of GPIO. It has no relation to FPGA speed grade. Although different GPIO traces routing may affect SDRAM board compatibility. It may be worse or better - need to test.


It is one of the problems, it is not the only one. A slower speed grade is not specified to interface with DRAM at the higher frequencies, even if it is integrated on board. A higher speed grade has more chances to operate at the higher frequencies and might compensate for a slower DRAM chip. Of course, if signal integrity is too bad, it might not help. But assuming signal integrity is about the same, the DE0 nano is faster and will certainly tolerate a slower DRAM at a given frequency.

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Re: MISTer on DE0-nano?

Postby olin » Wed Dec 06, 2017 7:29 pm

I got the boards today from allpcb.com. Total cost was $5.45 ($0.45 was paypal transaction fee) for 10 of those including shipping (I still think it was not intentional, or maybe it was some sort of discount I was not aware of when I made the order).

First mechanical test is here: http://mujweb.cz/molej/mister/pic/mech_test_02b.jpg

All looks good so far, everything fits where it should... away to do some soldering..

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Re: MISTer on DE0-nano?

Postby Sorgelig » Wed Dec 06, 2017 11:38 pm

Would be interesting to see max speed of this SDRAM chip you can achieve in memtest core.

P.S.: ah, it's 16MB chip.. Note: it has 12 address pins instead of 13 on 32MB/64MB chips. You will need to change the SDRAM HDL modules to work with reduced address bus.

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Re: MISTer on DE0-nano?

Postby olin » Sat Dec 09, 2017 12:16 am

Sorgelig wrote:Would be interesting to see max speed of this SDRAM chip you can achieve in memtest core.

I've recompiled memtest, but I think by default it is configured to 167MHz. Currently testing Winbond w9825g6jh-6 SDRAM that I desoldered from a board in my junk box. On 167MHz it behaves weirdly, first minute under the test it prints tons of errors, after that it is 'stable' for ~10 seconds, then increases error count by one, then it's stable for anther ~10 seconds, adds 1 error etc. When I start the test over it behaves the same.

I also compiled the 114 MHz version from your previous commit and that frequency seems more stable (0x14 errors in 25 minutes). So the SDRAM looks promising (I might have damaged the chip during desoldering though...).

It would be great if you could regenerate those qip pll.* files for different frequencies and commit them in different branches or whatever is most convenient for you. I could then build these different frequency rbfs and do more tests.

Sorgelig wrote:P.S.: ah, it's 16MB chip.. Note: it has 12 address pins instead of 13 on 32MB/64MB chips. You will need to change the SDRAM HDL modules to work with reduced address bus.

That's correct, I bought few extras for experiments (soldering and timing) I also have the same one in 32MBytes. Also I found some other junk boards with Etrontech EM639165TS-6G (16MB only) and also ESMT M12L25616A (unknown speed, the marking on the chip vanished). I'll eventually solder them for tests.
12 address pins - OK, I can see 'parameter DRAM_ROW_SIZE = 13' in memtest.sv, so I'll experiment with that. Thanks for the tip.

edit: fixed the boot issue. Embarrassingly it was the wrong placement of the buttons so they were always pushed and pulling some gpios down. Once I've repositioned the buttons (painstakingly desolder them) the issue was solved. I also found few lesser issues with the board: missing ground connection on the outer shield of VGA connector (hack fixed on the board), C9 was completely missing(!) but easy fix was to solder it on the bottom ground plane to an exposed track. The public fixes of the IO board for de0-nano-soc will follow soon.

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Re: MISTer on DE0-nano?

Postby olin » Sat Dec 09, 2017 9:11 pm

With the IO board the Winbond SDRAM works better (3 errors during an hour test on 114 MHz) compared to testing with my protoboard, that's somehow usable at least for basic tests of cores (ZX Spectrum core now works). I soldered second SDRAM board with ESMT chip (32MB from the junk board) - so far no luck even on 114MHz there is plenty of errors.

I've updated the design file on github, put the missing caps and some other minor tweaks. Still maintained to keep the board single sided (SDRAM exception).

io board v. 02c preview: https://github.com/ole00/hardware_miste ... render.png

I'd like to test IO board SD card reader - is there a core that uses it?

Edit: just looking at my footprint of the SDRAM IC - the pads are too long, I think that might contribute to some of the errors. Sorgelig's design has the pad much shorter. Next iteration I'll redo the footprint and halve the pads size for SDRAM.

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Re: MISTer on DE0-nano?

Postby NML32 » Sat Dec 09, 2017 9:26 pm

olin wrote:I'd like to test IO board SD card reader - is there a core that uses it?


https://github.com/MiSTer-devel/Main_Mi ... ry-SD-card

Per the Wiki:
Following cores require the secondary SD card:

MSX
Atari 800
Atari 5200
Sharp X68000
Sinclair QL (not confirmed yet)
More cores will support the secondary SD card.

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Re: MISTer on DE0-nano?

Postby Sorgelig » Sun Dec 10, 2017 1:04 am

olin wrote:Edit: just looking at my footprint of the SDRAM IC - the pads are too long, I think that might contribute to some of the errors. Sorgelig's design has the pad much shorter. Next iteration I'll redo the footprint and halve the pads size for SDRAM.

May be DE0 with your SDRAM board require other timings in sys_top.sdc in order to work on higher speeds. Also you need exactly AS4C16M16SA-6TCN chip if you want to reach acceptable speed.

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Re: MISTer on DE0-nano?

Postby ijor » Sun Dec 10, 2017 1:59 am

Perhaps more important than changing the constrains is to adjust the PLL clock shift. The ideal shift depends on several factors. You might also try using a dedicated clock output pin if it reaches a reasonable location on the GPIO connector.

The AS4C16M16SA-6TCN is certainly outstanding. You need a 200MHz speed grade (-5) from other vendors to match the specifications of this chip.


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