I have checked in a correction to VSYNC timing and to RCR timing (separate check-ins at https://github.com/dshadoff/TurboGrafx16_MiSTer
Based on measurements from a real machine, VSYNC interrupt occurs at the transition from HDS to HDW on the first non-visible scanline.
Also, RCR interrupt occurs about 12-13 VDC cycles before the end of HDW, as the render engine prepares the final display pixels.
More discussion on these timings can be found here:http://pcengine.proboards.com/thread/906/looking-info-video-wizard?page=1&scrollTo=12272
In making these changes, several issues were fixed as previously mentioned.
However, I noticed that some other measurements are still off, and there were some new issues introduced - notably, a change in behaviour during the introduction to Bomberman '94.
In order to reduce the visual impact of these changes, I set the RCR interrupt to 11 cycles before the end of HDW, and one line early (leaving comments to go back and fix once other timings are corrected).
In order to correct other timings, it looks like the video engine will need to properly observe all of the video controller register settings, instead of calculating many of its own values as it does today (plus some other timing corrections).
For example, HDS is currently calculated by MiSTer in order to centre the image on HDMI and VGA, but on the original system it is set by games to ensure proper placement on the original screens; signal timing happens as a consequence. (if correcting this results in off-centre images on HDMI, there can always be a post-processing layer added if necessary).
Sorgelig, is this what you meant by "need a full rewrite" ? Measuring and adjusting timings like this ? Or is there another deeper infrastructure layer underneath which also needs attention ?
I don't mind doing incremental work like this; I just want to know what I'm getting myself into.