Core porting questions

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Core porting questions

Postby Newsdee » Mon Sep 18, 2017 3:29 pm

Does anybody know what this error means?

Code: Select all

Error (12006): Node instance "cpu" instantiates undefined entity "GBse"


I think I've included all files (gameboy core, this one is from gb.v). The error is also confusing because I'd expect "GBse" is the name, and cpu the object/module?

I did follow the instructions from this page: https://github.com/MiSTer-devel/Main_Mi ... ting-notes
And defined "LITE" to bypass the upscaler (which hopefully will allow me to compile with a free version of Quartus)

I don't expect I can port the SD card handling, but if I can at least get the core to boot it would be a start.

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Re: Core porting questions

Postby Sorgelig » Mon Sep 18, 2017 4:29 pm

It looks like GBse module is missing or not declared. If cpu module is VHDL and GBse is Verilog, then cpu should include GBse component declaration.
You can check C64 core which is written in VHDL and includes some Verilog modules.

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Re: Core porting questions

Postby Newsdee » Tue Sep 19, 2017 1:57 pm

I managed to remap a few things, but how are we supposed to port OSD functions?
  • I suppose the video_ and VGA_ will go into "emu"?
  • Also does the SPI needs changing into something else?

Code: Select all

// include the on screen display
osd #(16,0,4) osd (
   .pclk       ( clk32       ),
   // spi for OSD
   .sdi        ( SPI_DI       ),
   .sck       ( SPI_SCK      ),
   .ss         ( SPI_SS3      ),
   .red_in  ( video_r      ),
   .green_in ( video_g      ),
   .blue_in  ( video_b      ),
   .hs_in     ( video_hs     ),
   .vs_in     ( video_vs     ),
   .red_out    ( VGA_R        ),
   .green_out( VGA_G        ),
   .blue_out   ( VGA_B        ),
   .hs_out      ( VGA_HS       ),
   .vs_out      ( VGA_VS       )
);


I'm also a bit lost with the DAC; the implementation of the core is very different to the module inside /sys/.
I suppose AUDIO_L and _R goes into "emu" as well, but what aobut ldatasum and rdatasum?

Code: Select all

sigma_delta_dac dac (
   .CLK      ( clk32          ),
   .ldatasum   ( audio_left[15:1]   ),
   .rdatasum   ( audio_right[15:1]   ),
   .left      ( AUDIO_L         ),
   .right   ( AUDIO_R      )
);


Sorry if some of it is obvious, I'm just trying to rewire things hoping it might work...

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Re: Core porting questions

Postby Sorgelig » Tue Sep 19, 2017 3:29 pm

Remove OSD from the core. It's handled and overlayed in top-level module (in /sys)

MiSTer requires 16-bit data for AUDIO_L/R signals unlike MiST where 1-bit used. So, remove the sigma_delta_dac and use this:

assign AUDIO_L = audio_left[15:0];
assign AUDIO_R = audio_right[15:0];
assign AUDIO_S = 0 or 1 depending if samples unsigned or signed.

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Re: Core porting questions

Postby Newsdee » Wed Sep 20, 2017 2:15 am

Thanks, I can compile now but I get a blank screen in VGA. I guess I need to assign the VGA signals as well?

eg.
assign VGA_R = video_r;

Also I guess I will need to change PLL settings for Clock50 instead of Clock27. I found a section with things like "27929 ps" which I think are timing related? In that case would it be expected to halve those values?

I have a naive hope wiring and timing adjustments will be enough. Probably not but gotta start somewhere :)

Edit: I realized ps means picoseconds so I guess the number should be higher to slow down the 50Mhz clock more. Googling the gameboy CPU frequency I would need to divide by 11.921 (roughly).

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Re: Core porting questions

Postby Sorgelig » Wed Sep 20, 2017 4:32 am

In PLL wizard it's enough just change the input frequency - everything else should be adjusted automatically. If original FPGA is not an Cyclone V, then you will need to create PLL from ground using the same output frequencies in settings.

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Re: Core porting questions

Postby Newsdee » Thu Sep 21, 2017 3:55 am

So I recreated the PLL and I wired the video output to emu. I get a VGA video signal now but... it is blank. At least it is roughly in range; it wasn't when I first used the original PLL.

Do I need to do something to get the OSD to respond (i.e. wire it sonewhere) Or if it doesn't, do I have something fundamentally wrong?

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Re: Core porting questions

Postby Sorgelig » Thu Sep 21, 2017 6:23 am

It's hard to tell where is problem. To get OSD working, core has to supply the video clock, system clock (through hps_io), VGA_DE and CE_PIXEL in addition to standard color and sync signals used in MiST. It's because top module has to process the video further and add OSD overlay. I've wrote about it in porting notes.
Why core doesn't display the video - it also depend on many factors depending on core code.

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Re: Core porting questions

Postby yellperil » Mon Sep 25, 2017 1:15 pm

Hi this is more of a core compilation question. I've downloaded Quartus Prime Lite 17.0 ( update 2 ) and am attempting to compile the C64 core.

But it's getting an error like there is maybe a file missing.

Warning (125092): Tcl Script File sys/vip/synthesis/vip.qip not found
Info (125063): set_global_assignment -name QIP_FILE sys/vip/synthesis/vip.qip -qip sys/vip.qip


then later on. . .

Error (12006): Node instance "vip" instantiates undefined entity "vip". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Info (144001): Generated suppressed messages file C:/Users/Michael Fong/Documents/yellperil_mister/C64_MiSTer/output_files/C64.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 4 warnings
Error: Peak virtual memory: 785 megabytes
Error: Processing ended: Mon Sep 25 21:15:08 2017
Error: Elapsed time: 00:00:19
Error: Total CPU time (on all processors): 00:00:38
Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 4 warnings


Anyhow any help would be appreciated.

Cheers,
MF

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Re: Core porting questions

Postby azesmbog » Mon Sep 25, 2017 3:32 pm

yellperil wrote:Anyhow any help would be appreciated.

Quartus -> Tools -> Qsys -> File -> Open...-> catalog sys -> vip.qsys Open -Generate HDL.. -> Finish
Processing -> Start Compilation
VIOLA!!

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Re: Core porting questions

Postby yellperil » Tue Sep 26, 2017 4:35 am

Awesome worked a treat!

Now I can't generate the rbf file.

I noticed that no rbf file is generated after compilation completes
I've tried to use File ==> Convert Programming File to convert the file c64_time_limited.sof.
I can't seem to add the .sof file to the tool. I can select it but it won't add.

Or is there a setting to stop this . . .

Info (115017): Design contains a time-limited core -- only a single, time-limited programming file can be generated
Last edited by yellperil on Tue Sep 26, 2017 5:11 am, edited 1 time in total.

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Re: Core porting questions

Postby Sorgelig » Tue Sep 26, 2017 5:09 am

yellperil wrote:Awesome worked a treat!

Now I can't generate the rbf file.

I noticed that no rbf file is generated after compilation completes
I've tried to use File ==> Convert Programming File to convert the file c64_time_limited.sof.
I can't seem to add the .sof file to the tool. I can select it but it won't add.

Or am I doing this wrong.

read about Full/Lite revisions

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Re: Core porting questions

Postby yellperil » Tue Sep 26, 2017 6:05 am

-- deleted --

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Re: Core porting questions

Postby Newsdee » Tue Sep 26, 2017 9:53 am

you can skip the VIP stuff by switching to the "LITE" version of the project, there should be a drop-down at the top.

It kills the HDMI output but it also compiles quickly. So good for development anyway.

On my side I managed to compile but no boot. I think I'll attempt a simpler core first...

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Re: Core porting questions

Postby udo » Sun Oct 15, 2017 9:52 am

Hi,

I somehow managed to compile the Mist core using porting guide. So far I have no IO-Board (hopefully coming soon), so no VGA-Output to do any tests.
But I am sure it will not work because of the way the Mist wants to talk to the ARM. Currently Mist wants to use several SPI channels, but Mister has another way to communicate. The porting guide did not help here. How did the other cores migrate from SPI to the new way?
The second thing which causes some trouble are the sdram controller and the scandoubler. For now I just used the sdram controller of Mist (not from the Framework) and instanciated the scandoubler with some dummy parameter (Mist had an different scandoubler that has no parameters needed).

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Re: Core porting questions

Postby Sorgelig » Sun Oct 15, 2017 10:37 am

SPI interface on MiST is used in user_io(mist_io), osd and data_io modules usually. You need replace these modules by hps_io from MiSTer. OSD is handled in framework - so simply remove OSD from ported core.
So, SPI should disappear from ported core. If it still used in other modules, then it will require more work.

Actually, porting the core is not a simple task ;)

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Re: Core porting questions

Postby udo » Sun Oct 15, 2017 11:07 am

Sorgelig wrote:SPI interface on MiST is used in user_io(mist_io), osd and data_io modules usually. You need replace these modules by hps_io from MiSTer. OSD is handled in framework - so simply remove OSD from ported core.
So, SPI should disappear from ported core. If it still used in other modules, then it will require more work.

Actually, porting the core is not a simple task ;)


I already removed the Mist OSD, but some of the components (video, dma and userio) still want to use spi. I think the Minimig Core had similar problems, so I will have a look what You did there ...

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Re: Core porting questions

Postby Sorgelig » Sun Oct 15, 2017 11:51 am

Which core are you porting?
Minimig is pretty complex core. Not good thing for study. Look in something simple like ZX core.

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Re: Core porting questions

Postby udo » Sun Oct 15, 2017 12:09 pm

Sorgelig wrote:Which core are you porting?
Minimig is pretty complex core. Not good thing for study. Look in something simple like ZX core.


I am trying the only core I am really interested in, the Mist core (ATARI-ST).

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Re: Core porting questions

Postby Sorgelig » Sun Oct 15, 2017 1:03 pm

udo wrote:I am trying the only core I am really interested in, the Mist core (ATARI-ST).

It will be a hard work.
MiST core is similar to Minimig - it has very special support on ARM side. It also uses many custom commands over SPI.
Although i've ported ARM part of MiST to MiSTer, this part of code was never tested and most likely requires tweaking/patching.
FPGA part will require special re-work as well since it's not generic core.
Anyway, i hope you will mange it since I never had Atari and don't know its hardware.

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Re: Core porting questions

Postby udo » Tue Oct 17, 2017 5:02 pm

Sorgelig wrote:
udo wrote:I am trying the only core I am really interested in, the Mist core (ATARI-ST).

It will be a hard work.
MiST core is similar to Minimig - it has very special support on ARM side. It also uses many custom commands over SPI.
Although i've ported ARM part of MiST to MiSTer, this part of code was never tested and most likely requires tweaking/patching.
FPGA part will require special re-work as well since it's not generic core.
Anyway, i hope you will mange it since I never had Atari and don't know its hardware.


Yes I already noticed that this will not just be a coppy and paste task ...
My first goal is to bring up the OSD-Display using the Framework. I think therefore I need to create and wire a instance of video_mixer (which will not automagically be created by the Framework).
This should at least remove those warnings (that probably prevent the OSD from working):

Warning (10034): Output port "CE_PIXEL" at mist_topde10n.v(28) has no driver
Warning (10034): Output port "VGA_DE" at mist_topde10n.v(39) has no driver

Probably Newsdee has similar problems with his core, because in the porting guide is not noted that video.sv (ZX-Spectrum) has some adaptations that are needed too. Newsdee, did You check for Warnings like the ones above? I think they can not be ignored.

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Re: Core porting questions

Postby azesmbog » Tue Oct 17, 2017 7:51 pm

udo wrote:
Warning (10034): Output port "CE_PIXEL" at mist_topde10n.v(28) has no driver
Warning (10034): Output port "VGA_DE" at mist_topde10n.v(39) has no driver


assign VGA_DE = 1;
assign pixel_clock = vga_clk;
only VGA/no menu

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Re: Core porting questions

Postby Sorgelig » Tue Oct 17, 2017 8:20 pm

azesmbog wrote:
udo wrote:
Warning (10034): Output port "CE_PIXEL" at mist_topde10n.v(28) has no driver
Warning (10034): Output port "VGA_DE" at mist_topde10n.v(39) has no driver


assign VGA_DE = 1;
assign pixel_clock = vga_clk;
only VGA/no menu


Not a good suggestion. Actually i've explicitly wrote the meaning of these signals in my porting guide.

Well, porting doesn't mean copy/paste from MiST to MiSTer. It requires some work.

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Re: Core porting questions

Postby Newsdee » Wed Oct 18, 2017 2:49 am

udo wrote:Probably Newsdee has similar problems with his core, because in the porting guide is not noted that video.sv (ZX-Spectrum) has some adaptations that are needed too. Newsdee, did You check for Warnings like the ones above? I think they can not be ignored.


I'm an HDL/EE beginner so I'm a bit out of depth here unfortunately. I hoped some code diffs of MiST vs MiSTer could give me insights and I vaguely get what is needed at a high level, but I'm a bit lost as to how to do that (e.g. rewrite top level to use OSD, kind of did that, but debugging seems difficult).

Honestly I think I need to try something simpler (say the MiST tutorials) before I move to a core...

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Re: Core porting questions

Postby udo » Wed Oct 18, 2017 6:00 am

Sorgelig wrote:
azesmbog wrote: assign VGA_DE = 1;
assign pixel_clock = vga_clk;
only VGA/no menu


Not a good suggestion. Actually i've explicitly wrote the meaning of these signals in my porting guide.

Well, porting doesn't mean copy/paste from MiST to MiSTer. It requires some work.


Oh thanks I missed the hints in the Porting guide. So they are "only" needed for the hdmi scaler? VGA Output should work without them too?
So far I can not try it on target, because my IO-Board is still not here ...


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