Built-in DDR3 memory has hardware controller and it's shared between ARM and FPGA. On FPGA side you have a nice convenient interface which is close to SRAM interface. So you don't have to worry about SDRAM complexity at all. Also you don't need to worry about refresh. Everything is done automatically on hardware level.
So, from first sight, it looks exciting. Evil comes when you start to use it. Soon you will realize that response time is pretty bad. Response time is not stable and varying from acceptable to unacceptable ranges, so even ZX Spectrum on standard 3.5MHz speed cannot be implemented.
Retro systems have used Asynchronous EDO DRAM. Although it was slow RAM, it provided a fixed access time for any RAM cell. Starting from SDR SDRAM chips started to use a burst transfer where access to a single cell takes almost the same time as access to 4-8 sequential cells. If system is optimized to access to a group of cells then it's much faster with SDRAM. Manufacturers started to rate the speed based on burst access and show a very big numbers like 10-20 times faster, but random access remained at the same level as old Async.DRAM.. So, if system access the RAM randomly by single cells then SDRAM is not faster at all. It even can be slower because requires a lot of clock cycles from starting access to get a first data.
When memory migrated from SDR to DDR, the burst became even longer and more cycles required to get the data. Thus even DDR3 on DE10-nano has whooping 800MHz clock, it's slower than DRAM on old good ZX Spectrum in terms of random single cell access
While relatively old SDR SDRAM also has same problem, it's still faster than DDR3 with random access. So, SDR SDRAM is still useful for many tasks where DDR cannot fit. That's why still many FPGA boards from Terasic have SDR SDRAM additionally to DDR SDRAM.