Minimig RTG possible?

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Minimig RTG possible?

Postby djmartins » Wed Jan 09, 2019 7:34 am

I am a big amiga fan and see a lot of FPGA stuff for them these days.
Here is a graphics card using a FPGA and Verilog:
https://github.com/mntmn/amiga2000-gfxcard

Would this code be of any use in adding it to the minimig core?
It is basically a Picasso96 clone and I see that FPGA Arcade Replay has a RTG core:
http://www.fpgaarcade.com/kb/setting-up ... picasso96/
BUT I am not seeing the source code for that one anywhere...
I'd love to see a higher end Amiga on MiSTer but realize it isn't a trivial task at all.

Any rumors of some Amiga FPGA guy getting in MiSTer?

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Re: Minimig RTG possible?

Postby Sorgelig » Wed Jan 09, 2019 5:17 pm

FPGAArcade never released the sources of Minimig.
RTG is definitely possible, just need someone very knowledgeable in Amiga hardware and drivers to implement it.

That FPGA card is definitely can be a starting point of RTG. It will need some redesign to use DDR3 instead of SDR SDRAM and some other tweaks probably.

It's kind of frustrating that pretty much alive Amiga community cannot find self-motivated HDL developer to perfect the Minimig.

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Re: Minimig RTG possible?

Postby Newsdee » Thu Jan 10, 2019 12:16 am

Sorgelig wrote:It's kind of frustrating that pretty much alive Amiga community cannot find self-motivated HDL developer to perfect the Minimig.

I suppose there is still an aversion to open source work, or concern that somebody will take an open source project and try to commercialize it without contributing (which has happened with earlier versions of Minimig).

That said, the current core is pretty great. I'm very grateful for all the work many people put into it. This version is the most likely to survive and get improvements in the future.

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Re: Minimig RTG possible?

Postby JimDrew » Thu Jan 10, 2019 12:28 am

Sorgelig wrote:FPGAArcade never released the sources of Minimig.


The FPGA Arcade Replay's core is not based on Minimig.

If you want to implement a frame buffer, I can make the RTG driver. We will need a vertical blank interrupt and 4MB of memory.
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Re: Minimig RTG possible?

Postby ijor » Thu Jan 10, 2019 2:25 am

Sorgelig wrote:It's kind of frustrating that pretty much alive Amiga community cannot find self-motivated HDL developer to perfect the Minimig.


Seems, like you said, the Amiga scene is too dominated by the commercial side. I guess that it will eventually happen, and might be even from an outsider. I guess Mike will eventually release his version.
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Re: Minimig RTG possible?

Postby JimDrew » Thu Jan 10, 2019 7:43 pm

BTW, to support Picasso96 the 4MB of video memory needs to be within the Amiga's memory map. Typically, Zorro III space. I don't think you can use the DDR3 memory for this unless you plan on transferring the Amiga memory to the DDR3 memory. For the replay driver, I used 4MB at a 64KB aligned block region. The alignment is a requirement of the Picasso96 software.
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Re: Minimig RTG possible?

Postby Sorgelig » Thu Jan 10, 2019 7:58 pm

I didn't get why DDR3 cannot be used in Amiga memory space.

I don't know what's the requirement of video hardware for Picasso96. If it's just plain video buffer mapped at some address space then ist's very easy to implement. If it requires some hardware acceleration like blitter then i need to see some doc with registers and their functions, so i can evaluate the complexity.

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Re: Minimig RTG possible?

Postby ijor » Fri Jan 11, 2019 1:42 am

JimDrew wrote:BTW, to support Picasso96 the 4MB of video memory needs to be within the Amiga's memory map. Typically, Zorro III space. I don't think you can use the DDR3 memory for this unless you plan on transferring the Amiga memory to the DDR3 memory.


Jim, the FPGA can map some address range to SDRAM and other range to DDR without much problems. At least in theory, you can implement any kind of combination that you want.
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Re: Minimig RTG possible?

Postby ex68k » Fri Jan 11, 2019 2:52 pm

Newsdee wrote:I suppose there is still an aversion to open source work, or concern that somebody will take an open source project and try to commercialize it without contributing (which has happened with earlier versions of Minimig)..

Specially, when you get asked for help, getting the commercial version to work, because they don't offer any support :(

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Re: Minimig RTG possible?

Postby ex68k » Fri Jan 11, 2019 2:54 pm

Sorgelig wrote:I didn't get why DDR3 cannot be used in Amiga memory space.
I don't know what's the requirement of video hardware for Picasso96. If it's just plain video buffer mapped at some address space then ist's very easy to implement. If it requires some hardware acceleration like blitter then i need to see some doc with registers and their functions, so i can evaluate the complexity.

Amiga has some weird timing issues, and the latency on DDR3 is to high. (?)
Actually, it isn't, as the vampire4 has DDR3, and they got it to work.

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Re: Minimig RTG possible?

Postby ex68k » Fri Jan 11, 2019 2:59 pm

Sorgelig wrote:It's kind of frustrating that pretty much alive Amiga community cannot find self-motivated HDL developer to perfect the Minimig.

There are some people working on it, but very slowly, and they got tired of the discussion around it, so they just continue in the dark, before showing anything. It is really funny, how unfriendly the tone in the amiga forums is sometimes.

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Re: Minimig RTG possible?

Postby PurpleMelbourne » Fri Jan 11, 2019 3:44 pm

ex68k wrote:It is really funny, how unfriendly the tone in the amiga forums is sometimes.

Yeah I noticed that too...

Hey Sorgelig, I don't know where it is in the ROM Kernel Reference Manuals, but I do have on hand some good documentation from Davie Haynie's blog. These are the documentation proposal for the Acutiator 4th generation Amiga with details about the "older Amiga" hardware which you want to know.

Here is the proposal for the Acutiator 4th generation Amiga.
On Chapter 2 page 8 there is a memory map which might be helpful.
http://www.thule.no/haynie/research/acutiatr/docs/acu1.pdf

The ROM Kernel Reference Manuals (but I haven't gone through these to confirm its all good)
https://newbooksinpolitics.com/political/amiga-rom-kernel-reference-manual/

Hope this helps.

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Re: Minimig RTG possible?

Postby JimDrew » Fri Jan 11, 2019 4:07 pm

ijor wrote:
JimDrew wrote:BTW, to support Picasso96 the 4MB of video memory needs to be within the Amiga's memory map. Typically, Zorro III space. I don't think you can use the DDR3 memory for this unless you plan on transferring the Amiga memory to the DDR3 memory.


Jim, the FPGA can map some address range to SDRAM and other range to DDR without much problems. At least in theory, you can implement any kind of combination that you want.


Ah, in that case then maybe there is no issue. I am just going off my experience with what the Replay required.

There is no blitter requirement for RTG, although I can support that if there is a blitter engine. Mike made a very slick blitter engine for the Replay's Amiga RTG. There is source, destination, modulo, and blit type. You set the source, modulo, and blit type first and the last byte of the destination address triggers the blit operation.
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Re: Minimig RTG possible?

Postby Sorgelig » Fri Jan 11, 2019 8:04 pm

PurpleMelbourne wrote:
ex68k wrote:It is really funny, how unfriendly the tone in the amiga forums is sometimes.

Yeah I noticed that too...

Hey Sorgelig, I don't know where it is in the ROM Kernel Reference Manuals, but I do have on hand some good documentation from Davie Haynie's blog. These are the documentation proposal for the Acutiator 4th generation Amiga with details about the "older Amiga" hardware which you want to know.

Here is the proposal for the Acutiator 4th generation Amiga.
On Chapter 2 page 8 there is a memory map which might be helpful.
http://www.thule.no/haynie/research/acutiatr/docs/acu1.pdf

The ROM Kernel Reference Manuals (but I haven't gone through these to confirm its all good)
https://newbooksinpolitics.com/political/amiga-rom-kernel-reference-manual/

Hope this helps.


Thanks for book!
Second link requires registration with credit card - no way i will register such strange site.

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Re: Minimig RTG possible?

Postby Alynna » Fri Jan 11, 2019 9:23 pm

Forgive if this is necroposting but what is stopping anyone from exposing the framebuffer as a Zorro III card?
Will require 68020 for sure, but then you can have the card anywhere in the 32bit space.

As soon as my IO card arrives with the SDRAM, i'm going to get Minimig AGA on my project list (I have the DE10 Nano already).
I'm also interested in experimenting with adding a 1280x800 *Native* line mode (basically double speed Super High Res interlaced only without the interlace) and 640x480/512 non-interlaced modes, but note they would be *brand new modes*. I don't know how feasable it is yet tho.

640x480/512 non-interlaced: 31khz, outputs native to VGA
1280x800/1024 non-interlaced: 62khz, outputs native to HDMI, probably would work on SVGA monitors with at least 768 lines

I'm thinking of moving some lines around from what I have seen. Probably should go for (OMG edited for Amiga expansion compliance):
4mb chip ($000000-3FFFFF)
4mb fast ($400000-7FFFFF)
24mb 32 bit fast ($1000000-$27FFFFF) - This is A3000 motherboard RAM space and is a good place to expand the SDRAM into
16mb Z3 P96 ($10000000-$10FFFFFF) Might as well support those Big Modes (like 1920x1080x32: requires 8.2mb RAM)
496mb Z3 Expansion RAM (from the HPS) ($11000000-$2FFFFFFF) - expose as a Z3 RAM expansion so the latency doesn't matter so much.

Just noticed this:

Code: Select all

# cat /proc/iomem
00000000-1fefffff : System RAM
  00008000-00a92873 : Kernel code
  00b14000-00c0ad7b : Kernel data

Edited memory map to expect 512mb of available HPS RAM

Latest MiSTER firmware already chops away 512m of the DDR3 RAM for cores (HPS addresses $20000000-3FFFFFFF apparently), so could in theory have even more "Zorro III RAM"

P96 could be from the HPS DDR3 (latency won't matter as much on the framebuffer)

Most things, actually, if they're being interfaced from the HPS side, could just be brought in as expansions which can play alot looser with the timing rules.

Also from my looking at the vhdl so far and the HPS interface given it shouldn't be *too* difficult to set up a SANA-II device over the HPS.

The cores i'm most interested in improving is the Amiga core and i'm also working on my own core ( for a completely new architecture I want to make :D )

BTW is there a chat place (discord/telegram/irc/etc) where we talk about all things MiSTer?
Last edited by Alynna on Fri Jan 11, 2019 10:04 pm, edited 6 times in total.

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Re: Minimig RTG possible?

Postby Alynna » Fri Jan 11, 2019 9:34 pm

ex68k wrote:
Sorgelig wrote:I didn't get why DDR3 cannot be used in Amiga memory space.
I don't know what's the requirement of video hardware for Picasso96. If it's just plain video buffer mapped at some address space then ist's very easy to implement. If it requires some hardware acceleration like blitter then i need to see some doc with registers and their functions, so i can evaluate the complexity.

Amiga has some weird timing issues, and the latency on DDR3 is to high. (?)
Actually, it isn't, as the vampire4 has DDR3, and they got it to work.


Vampire is a special card. I've got one in my A1000.
Don't expect to be able to make Minimig as good as Vampire, their DDR3 is wired to the FPGA quite different and does not have to go through the HPS to be accessed.

From what I see in the VHDL sources, it looks like DDR3 interface is actually very fast, but it does 64 bit transfers. If it takes 6 (for example) cycles or something to do that access, it will take 6 cycles to transfer any amount of data from 8 to 64 bits, which is where the latency comes from. Might be wrong about this, its just what I interpreted from the code. This is why it is not suitable for retro cores, because theres LOTS of random, 8 bit accesses which is very not-optimal for a 64 bit data path.

But this would mean in 6 cycles you could transfer 8 bytes which is faster than doing 1 byte per cycle. 32 bit modes would benefit from this most, if you make a little cache on the fpga itself to buffer your writes to the fpga and then transfer 8 bytes at a time it could be very good.

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Re: Minimig RTG possible?

Postby Sorgelig » Fri Jan 11, 2019 10:49 pm

Alynna wrote:BTW is there a chat place (discord/telegram/irc/etc) where we talk about all things MiSTer?

This forum is exactly about MiSTer. So talk here. If you will be an active MiSTer developer, then we can find some other place to talk.

It's wonderful that you are self-motivated to improve the Minimig! This core needs some internal improvements besides the new feature. This core has stability issue. So this is first thing need to be improved if you don't want to compile the core with different SEED values to find a working build :)

DDR3: 512MB is dedicated for FPGA but this memory is used for scaler as well. Scaler uses roughly 32MB at beginning of FPGA address space. There can be other buffers there (like planning Alsa audio buffer), so first 64MB should not be used. So, you have 448MB for your needs. Basically Amiga doesn't need more than 128MB. Ok, 256MB is like the top size for any imaginable needs.
DDR3 interface (MPFE) is very effective when burst is used. So it will be significantly faster than SDRAM if some cache for Fast RAM will be implemented. Even if no burst is used, simple prefetch of next 64bit word also speedup the access very much. So you can have about 16bytes cache for sequential access which will reduce the average latency.

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Re: Minimig RTG possible?

Postby Sorgelig » Fri Jan 11, 2019 11:22 pm

Btw, besides unisual 1280x800 i hope you will make standard resolution 1280x720 as well.

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Re: Minimig RTG possible?

Postby Alynna » Sat Jan 12, 2019 2:22 am

Sorgelig wrote:
Alynna wrote:BTW is there a chat place (discord/telegram/irc/etc) where we talk about all things MiSTer?

This forum is exactly about MiSTer. So talk here. If you will be an active MiSTer developer, then we can find some other place to talk.

I was thinking along the lines of a realtime chat like IRC, wondering if we had one already or not. We could set one up, but for all sorts of MiSTer talk not just development. It's suprising how much positive Amiga talk comes out of Atari forum too. :D I would suggest either a discord server or an IRC channel on Freenode.

I'll definitely be posting here too :) I'm planning on improving the Amiga core for sure (I have wanted to develop Amiga stuff since I was in my teens), and working on my own core ( https://public.kitsunet.net/832/Fox832MMAP.txt ), and I have some interest in adding virtual hardware to FPGA64 too. I don't know how active because of other activities, but i'll probably get the stuff I want to do, done :)

Sorgelig wrote:It's wonderful that you are self-motivated to improve the Minimig! This core needs some internal improvements besides the new feature. This core has stability issue. So this is first thing need to be improved if you don't want to compile the core with different SEED values to find a working build :)

I'm not sure I understand this part, whats wrong with it, and what are the SEED values in referent to?

Sorgelig wrote:DDR3: 512MB is dedicated for FPGA but this memory is used for scaler as well. Scaler uses roughly 32MB at beginning of FPGA address space. There can be other buffers there (like planning Alsa audio buffer), so first 64MB should not be used. So, you have 448MB for your needs. Basically Amiga doesn't need more than 128MB. Ok, 256MB is like the top size for any imaginable needs.
DDR3 interface (MPFE) is very effective when burst is used. So it will be significantly faster than SDRAM if some cache for Fast RAM will be implemented. Even if no burst is used, simple prefetch of next 64bit word also speedup the access very much. So you can have about 16bytes cache for sequential access which will reduce the average latency.


Lets try this memory map then:
4mb chip ($000000-3FFFFF) - I know this is nonstandard but Vamp V4 standalone is planning on doing it and more chip is needed
4mb fast ($400000-7FFFFF) - Some application straight up need 24 bit fast RAM
1mb slow ($C00000-CFFFFF) - This could actually come from HPS
24mb 32 bit fast ($1000000-$27FFFFF) - This is A3000 motherboard RAM space and is a good place to expand the SDRAM into
16mb Z3 P96 ($10000000-$10FFFFFF) Might as well support those Big Modes (like 1920x1080x32: requires 8.2mb RAM)
256mb Z3 Expansion RAM (from the HPS) ($2000000-$2FFFFFFF) - expose as a Z3 RAM expansion so the latency doesn't matter so much. Lets also put it further away from the P96 card :)

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Re: Minimig RTG possible?

Postby Alynna » Sat Jan 12, 2019 2:44 am

Sorgelig wrote:Btw, besides unisual 1280x800 i hope you will make standard resolution 1280x720 as well.


The reason that 1280x800 is a target is because of the corresponding NTSC/PAL modes that it is a good idea to keep timing with.

With Amiga native modes:
NTSC modes tend to be 320/640/1280 by 200
PAL modes tend to be 320/640/1280 by 240

The actual number of lines vary but also tend to be in the overscan area and not visible.
Interlaced modes are as above but rendering 400/480 lines instead.
In theory these modes can be de-interlaced by doubling the scan speed and rendering them progressive, but this does require development of a new mode (one that does not try to interlace the lines). But to keep timing it does have to be double the lines, meaning 400/480 lines.

Therefore to keep the timing right for an even higher mode, the next step would be to double the interlaced mode timing to go for 800/960 lines.
HOWEVER, you can still get a 1280x720 mode out of it. You can put 80 lines (40 on top 40 on bottom) into the overscan area. You'll still be rendering 800 lines in the core but only 720 would be displayed. Typically you'd use the "overscan" preference panel to not use the additional lines. But do note that many monitors (particularly full HD ones) can do 1280x800 mode, so people with higher mode monitors can use 1280x800 and 1280x960. :)

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Re: Minimig RTG possible?

Postby Alynna » Sat Jan 12, 2019 2:55 am

TL;DR on the last post is that real 16:9 modes are better for RTG, 16:10 are best targeted for NTSC and 4:3 for PAL, due to how Commodore originally designed the modes.

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Re: Minimig RTG possible?

Postby Sorgelig » Sat Jan 12, 2019 3:03 am

16:9 is standard for HDTV.
16:10 is old abandoned aspect ratio. Only chinese cheap monitors are still producing in odd resolutions like 1280x800. Many monitors may accept it but aspect ratio will be wrong. Although i have 1920x1200 monitor, today it's rather odd than normal resolution.

Not sure what you mean by 240/200 lines. If you are talking about magnification of original PAL/NTSC then it's one thing. But if you are talking about native resolutions, then there is no relation to PAL/NTSC SDTV resolution. Amiga is pretty much fine with 1280x720 HD resolution. It's just slow on AGA.
RTG timings won't fit into PAL/NTSC if you are talking about high resolutions.

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Re: Minimig RTG possible?

Postby Alynna » Sat Jan 12, 2019 3:19 am

Sorgelig wrote:16:9 is standard for HDTV.
16:10 is old abandoned aspect ratio. Only chinese cheap monitors are still producing in odd resolutions like 1280x800. Many monitors may accept it but aspect ratio will be wrong. Although i have 1920x1200 monitor, today it's rather odd than normal resolution.

Not sure what you mean by 240/200 lines. If you are talking about magnification of original PAL/NTSC then it's one thing. But if you are talking about native resolutions, then there is no relation to PAL/NTSC SDTV resolution. Amiga is pretty much fine with 1280x720 HD resolution. It's just slow on AGA.
RTG timings won't fit into PAL/NTSC if you are talking about high resolutions.


Now that I think about it there is a way to a 1280x720 native mode, which is PAL timing * 3 (240*3). However its corresponding timing for NTSC is 1280x800 which is seen nowhere. However this could potentially be rendered as 1024x600 (seen in a decent number of flat panels).

In the end if there is x3 modes (600/720) and x4 modes (800/960) there will be all the modes that come with them, other modes can be made by putting extra lines into overscan, but i'm pretty sure for native modes they have to be an integer multiplier of original NTSC/PAL modes to keep the timing right.

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Re: Minimig RTG possible?

Postby Alynna » Sat Jan 12, 2019 3:23 am

Maybe i'm missing something but I've never been about to get a 1280x720 resolution on anything but RTG... But the only thing I have right now that does AGA is the MiniMig MiST.. my "real Amiga" is an A1000 with a Vampire in it O.o

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Re: Minimig RTG possible?

Postby Sorgelig » Sat Jan 12, 2019 3:36 am

With monitor driver 720HD you can have 1280x720i50 resolution in Workbench with AGA chipset. Also 800x600 and 1024x768 modes are available. All of them are on standard AGA chipset. On real Amiga (and MiST) it requires special Commodore monitor supporting such non-standard resolution. On MiSTer it works through HDMI on any TV.

Still don't understand your obsession of following PAL/NTSC. RTG is VGA (and HDMI) output and has nothing to do with PAL/NTSC. So you need to follow VGA/HDMI resolutions instead. You cannot play regular games on RTG. Only specifically written for RTG games can work. And those working through Workbench video output subsystem.

And thanks to FPGA, both native and RTG video outputs can share the same video output.


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