TSconf port.

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ManuFerHi
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TSconf port.

Postby ManuFerHi » Mon Sep 02, 2019 12:19 pm

I'm trying to port this core, it's from u16 reverse FPGA, the core starts, but I can't get the keyboard to work, I've added the user_io wrapper, but the core has these connections for the PS / 2 keyboard.
-----------------------------------------------------------------------------
-- PS/2 Keyboard
signal kb_do_bus : std_logic_vector(4 downto 0);
signal kb_fn_bus : std_logic_vector(4 downto 0);
signal kb_joy_bus : std_logic_vector(4 downto 0);
signal key_scancode : std_logic_vector(7 downto 0);
signal kb_report : std_logic_vector(55 downto 0);
-----------------------------------------------------------------------------
I have seen that the normal thing is that the core has the PS / 2 clock and data connections, but in this core it is not like that and I don't know how to connect.
I tried to join the signal key_scancode with key_code of mist_io, but it doesn't work.
This core works on its original board with USB keyboard, via client-host connection and has a wrapper that converts usb scancodes to scancodes ps / 2 (key_scancode signal).
I'd appreciate some help ...
I share the files in case anyone wants to contribute.
http://www.mediafire.com/file/2puw3rh5t ... f.rar/file

slingshot
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Re: TSconf port.

Postby slingshot » Mon Sep 02, 2019 1:38 pm

Hi!

Good to see a new port1

I don't know which user_io you're using, but recent ones, like this:
https://github.com/mist-devel/fpgagen/b ... r_io.v#L73
exports the scan code directly (valid when key_strobe asserted).

Upd.: I see mentioned key_code. But isn't there any signal which indicates when a new scancode arrived?
Upd2.: you didn't connect clk_sys to user_io
Last edited by slingshot on Mon Sep 02, 2019 1:53 pm, edited 2 times in total.

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alexh
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Re: TSconf port.

Postby alexh » Mon Sep 02, 2019 1:42 pm

TSConf was ported to MiSTer? Perhaps there is some extra information there?

https://github.com/MiSTer-devel/TSConf_MiSTer/

ManuFerHi
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Re: TSconf port.

Postby ManuFerHi » Mon Sep 02, 2019 4:37 pm

True! I didn't connect clk_sys, thanks. I´m a newbie...

slingshot
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Re: TSconf port.

Postby slingshot » Mon Sep 02, 2019 5:12 pm

ManuFerHi wrote:True! I didn't connect clk_sys, thanks. I´m a newbie...

And most functions in user_io won't work without master clock :)
Old versions didn't require it, but also didn't transfer the signals from the SPI clock domain to the master clock domain safely.

ManuFerHi
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Re: TSconf port.

Postby ManuFerHi » Fri Sep 06, 2019 12:30 pm

I'm stuck. Now the keyboard works (although only the first time you press, it is always the same one pressed) although for now it helps me to continue I can not read the SD. The core starts, and tries to access the rom roms / zxevo.rom, as it does not find it, it tries to dump the rom from the spi flash, but of course ... the mist has no flash. Pressing enter to continue the core remains brick.
I have seen examples of several cores of how to implement the SD and I think I have done the same, but nothing does not read me the file, I leave here the TOP file in case someone sees the error.
Maybe I should make a new TOP instead of modifying the one there is.
You do not have the required permissions to view the files attached to this post.

slingshot
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Re: TSconf port.

Postby slingshot » Fri Sep 06, 2019 1:00 pm

I see you're using the SD-card wrapper. Is the core supports FAT FS? Or how is it supposed to find that .rom? If you turn on DIP SW1, then some debug info can be seen if you connect the ARM UART to a PC (like SD RD xxx where xxx is the LBA of the sector read).
And clk_sd for user_io should be identical to the clock used for the sd_card. I think clk_28mhz should be used everywhere, 84MHz is only for the SDRAM.

ManuFerHi
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Re: TSconf port.

Postby ManuFerHi » Fri Sep 06, 2019 11:26 pm

Sorry, I shared a bad link before.
Here the entire project > https://www.mediafire.com/file/ybsv9fex ... f.rar/file

Supports FAT32 to load roms and files, i´m connect same clock 28mhz to io_mist and sd_card, this afternoon I have redone everything in case I had left something but there is no result.

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Re: TSconf port.

Postby slingshot » Sat Sep 07, 2019 1:08 pm

I don't see CKE and nCS pins of the SDRAM connected. CKE should be '1', nCS '0'. Also allow_shdh for sd_card is missing.
Upd.: forgot that CKE is pulled up directly on the board. Still nCS should be pulled down explicitly. Otherwise I have no simple answer, the core should be debugged.
Upd2.: c1 is not a clock, but some derived signal from the PLL's generated 28MHz output. The PLL's c1 should be used as a clock for user_io and sd_card. Also a proper .sdc file is missing.


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