Actually it doesn't depend on the receiving CPU, but there's an oddity in the ATA spec itself:
Although most multi-byte fields in ATA are little-endian, some fields are unusual:
a) The IDENTIFY (PACKET) DEVICE data SERIALNUMBER field, MODELNUMBER field, and FIRMWAREREVISION field, and possibly the MEDIASERIALNUMBER field each contain ASCII characters representing an ASCII string. However, they do not contain the characters in normal string order (with the first character at byte 0, the second character at byte 1, etc.). For historical reasons, each pair of bytes is swapped (byte 0 with byte 1, byte 2 with byte 3, byte 4 with byte 5, etc.).
Yes, that's right - but we're not talking about the receiving CPU here - we're the sender!
That swapping happens automatically on a big-endian CPU (when the firmware's running on 68k) because the buffer's sent in 16-bit words, first the low byte then the high byte - so the text string "ABCD" is sent 'B', 'A', 'D', 'C'.
On a little-endian CPU (such as the MIST's onboard ARM) the same buffer is sent 'A', 'B', 'C', 'D', so needs to be byte-swapped.