Mister SNES port to MIST possible?

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Re: Mister SNES port to MIST possible?

Postby slingshot » Sat Nov 23, 2019 1:40 pm

NONETE wrote:
Tested in a Mistica via rgb and my sdram memory is Alliance , maybe that will help.

Only test 14 compiled with c0 at 1100 works estable in my mistica

I've uploaded the latest tweaks to the github repo, if you can compile it from there, you can experiment with phase shifts again. On my MiST it even accepts -1100 now (and passes the timing analysis + works, too). Or if you can spot some difference between the Hynix and Alliance datasheet, I'll look at it once more, but I really give up now.

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Re: Mister SNES port to MIST possible?

Postby ijor » Sat Nov 23, 2019 4:31 pm

NONETE wrote:To say what is the best value that works for me, without a doubt the 5 value works better but no well.
Tested in a Mistica via rgb and my sdram memory is Alliance , maybe that will help.
Only test 14 compiled with c0 at 1100 works estable in my mistica


Can you please post a high rez picture of your Alliance SDRAM chip.
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Re: Mister SNES port to MIST possible?

Postby ijor » Sat Nov 23, 2019 4:32 pm

slingshot wrote:I've uploaded the latest tweaks to the github repo, if you can compile it from there, you can experiment with phase shifts again. On my MiST it even accepts -1100 now (and passes the timing analysis + works, too). Or if you can spot some difference between the Hynix and Alliance datasheet, I'll look at it once more, but I really give up now.


It is probably not the brand, but the speed grade. According to some online pictures, seems MISTICA uses a faster SDRAM chip. A faster chip might produce hold timing violations at the FPGA inputs. This matches the results that a smaller negative shift works better for the user.

In theory, if you meet timing, and the constrains are compatible with faster chips, then it should work anyway. But, it is possible that the constraints are not exact and you are missing hold timing by a small degree. In practice this will still work because you almost never reach the worst conditions considered by timing analysis. Except when you have a faster chip. Again, a faster chip is better for setup timing and higher frequencies, but it is worse for hold timing.

Can you please post a Timequest I/O report, for both slow and fast conditions. Note that Timequest GUI process a single corner a time. I can of course compile the core and produce the reports myself. But your compilation might be slightly different for a variety of reasons. And I would prefer to see the report on your exact build.
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Re: Mister SNES port to MIST possible?

Postby DanyPPC » Sat Nov 23, 2019 5:11 pm

MiSTICA developer can submit the model and frequency of ram used in his product.

A memory tester program can be made to verify timing speeds, or I wrong ?

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Re: Mister SNES port to MIST possible?

Postby slingshot » Sat Nov 23, 2019 5:20 pm

ManuhFeri wrote it uses -6 speed grade Alliance module, which has: tOH = 2.5, tAC(3) = 5 vs the one in the Micron datasheet for -75: tOH = 2.7 and tAC(3)= 5.4.
Input setup/hold times are the same: 1.5/0.8

These are the first lines of IO report - for the slow 85C device model):

Code: Select all

Inputs to registers (setup)
0.224   SDRAM_DQ[2]   sdram:sdram|sd_din[2]   pll|altpll_component|auto_generated|pll1|clk[0]   pll|altpll_component|auto_generated|pll1|clk[1]   8.870   -0.574   1.241

hold
11.324   SDRAM_DQ[4]   sdram:sdram|sd_din[4]   pll|altpll_component|auto_generated|pll1|clk[0]   pll|altpll_component|auto_generated|pll1|clk[1]   -6.654   -0.232   1.113

registers to output (setup)
1.847   sdram:sdram|SDRAM_DQ[5]~en   SDRAM_DQ[5]   pll|altpll_component|auto_generated|pll1|clk[1]   pll|altpll_component|auto_generated|pll1|clk[0]   6.654   0.116   3.313

hold
2.340   sdram:sdram|SDRAM_DQ[12]~reg0   SDRAM_DQ[12]   pll|altpll_component|auto_generated|pll1|clk[1]   pll|altpll_component|auto_generated|pll1|clk[0]   -1.108   0.441   2.583


And slow 0C:

Code: Select all

Input setup:
0.062   SDRAM_DQ[2]   sdram:sdram|sd_din[2]   pll|altpll_component|auto_generated|pll1|clk[0]   pll|altpll_component|auto_generated|pll1|clk[1]   8.870   -0.770   1.213

Input hold:
11.542   SDRAM_DQ[7]   sdram:sdram|sd_din[7]   pll|altpll_component|auto_generated|pll1|clk[0]   pll|altpll_component|auto_generated|pll1|clk[1]   -6.654   -0.470   1.086

output setup:
2.533   sdram:sdram|SDRAM_DQ[5]~en   SDRAM_DQ[5]   pll|altpll_component|auto_generated|pll1|clk[1]   pll|altpll_component|auto_generated|pll1|clk[0]   6.654   0.358   2.869

output hold:
1.962   sdram:sdram|SDRAM_DQ[0]~en   SDRAM_DQ[0]   pll|altpll_component|auto_generated|pll1|clk[1]   pll|altpll_component|auto_generated|pll1|clk[0]   -1.108   0.668   2.432

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Re: Mister SNES port to MIST possible?

Postby ManuFerHi » Sat Nov 23, 2019 6:58 pm

Yes, i´m use the AS4C16M16SA-6TCN sdram memory. In snes core is estable at -(1000-1500ps) sdram clk phase. Others cores not have this issue.
As a curiosity, I am making a new FPGA, it is called SiDi, it has a slightly smaller FPGA and same firmware as mist, it is a very small 4-layer circuit the tracks from the sdram to the FPGA as soon as they reach 1-2cm are very Direct and well alienated and the core SNES I must put the same value (-1150ps) with micron memories there is no problem but unfortunately they are no longer manufactured.
Another curiosity, all the tested cores work well in SiDi, the only one that gives me problems is Genesis, in Mist the external one for clk sdram is at -0.77ns and in SiDi too many graphic glitches, for a more correct operation I had to put this phase at the same value as C0 and C2, now it works better but I still have some graphic glitch in some game.
https://github.com/ManuFerHi/SiDi-FPGA/wiki/TheBoard

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Re: Mister SNES port to MIST possible?

Postby ijor » Sat Nov 23, 2019 7:25 pm

slingshot wrote:ManuhFeri wrote it uses -6 speed grade Alliance module, which has: tOH = 2.5, tAC(3) = 5 vs the one in the Micron datasheet for -75: tOH = 2.7 and tAC(3)= 5.4.
Input setup/hold times are the same: 1.5/0.8


Yes, but I suspect the datasheets might be not 100% accurate about tOH for the faster speed grades, it might be smaller (worse)

These are the first lines of IO report - for the slow 85C device model):

Code: Select all

hold
11.324   SDRAM_DQ[4]   sdram:sdram|sd_din[4]   pll|altpll_component|auto_generated|pll1|clk[0]   pll|altpll_component|auto_generated|pll1|clk[1]   -6.654   -0.232   1.113
...


Slack can't be that good, and relationship can't be that negative. You have a wrong multicycle constraint for the hold relationship. Remove this line from the SDC file :

Code: Select all

#set_multicycle_path -from [get_clocks $sdram_clk] -to [get_clocks $mem_clk] -hold -end 1
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Re: Mister SNES port to MIST possible?

Postby slingshot » Sat Nov 23, 2019 8:24 pm

ijor wrote:
Slack can't be that good, and relationship can't be that negative. You have a wrong multicycle constraint for the hold relationship. Remove this line from the SDC file :

Code: Select all

#set_multicycle_path -from [get_clocks $sdram_clk] -to [get_clocks $mem_clk] -hold -end 1


It's worse, but still lot of room to play:

Code: Select all

3.562   SDRAM_DQ[4]   sdram:sdram|sd_din[4]   pll|altpll_component|auto_generated|pll1|clk[0]   pll|altpll_component|auto_generated|pll1|clk[1]   1.108   -0.232   1.113

And still stable on MiST :)

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Re: Mister SNES port to MIST possible?

Postby slingshot » Sat Nov 23, 2019 8:28 pm

ManuFerHi wrote:As a curiosity, I am making a new FPGA, it is called SiDi, it has a slightly smaller FPGA and same firmware as mist, it is a very small 4-layer circuit the tracks from the sdram to the FPGA as soon as they reach 1-2cm are very Direct and well alienated and the core SNES I must put the same value (-1150ps) with micron memories there is no problem but unfortunately they are no longer manufactured.

Would be interested with an EP4C55 and 64MB (maybe 2x64MB) SDRAM module (I know, that's way too expensive compared to a DE10-nano).
Upd.: why not a Cyclone10? 10CL055 is about the same price, and a higher speed grade is only slightly more expensive.

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Re: Mister SNES port to MIST possible?

Postby Gehstock » Sat Nov 23, 2019 8:41 pm

Had the same Idea :D

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Re: Mister SNES port to MIST possible?

Postby ManuFerHi » Sat Nov 23, 2019 8:45 pm

SiDi is a low cost version <100€, next step is a FGPA with EP4C55 with 32mb, but expansion port for extra sdram or others things, and hdmi output, It will not rise too much in price, the goal is to leave for 150€.

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Re: Mister SNES port to MIST possible?

Postby slingshot » Sat Nov 23, 2019 8:48 pm

ManuFerHi wrote:SiDi is a low cost version <100€, next step is a FGPA with EP4C55 with 32mb, but expansion port for extra sdram or others things, and hdmi output, It will not rise too much in price, the goal is to leave for 150€.

What's the problem with a Cyclone10? But if you can get the EP4C55 cheaper, then OK.

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Re: Mister SNES port to MIST possible?

Postby ManuFerHi » Sat Nov 23, 2019 8:51 pm

I had not thought Cyclone10, I see that the price does not rise too only about € 10, perhaps it is interesting.

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Re: Mister SNES port to MIST possible?

Postby ijor » Sat Nov 23, 2019 8:58 pm

slingshot wrote:It's worse, but still lot of room to play:

Code: Select all

3.562   SDRAM_DQ[4]   sdram:sdram|sd_din[4]   pll|altpll_component|auto_generated|pll1|clk[0]   pll|altpll_component|auto_generated|pll1|clk[1]   1.108   -0.232   1.113



Yes, but:

1 - This is with the smaller 1.1 shift that works better for them.
2 - This is not the fast corner. This is slow corner at low temp. Yes, you have to check the fastest corner even with the slowest FPGA speed grade.
3 - This is assuming the datasheet is accurate.
4 - You might have overestimated the minimum trace board delay.

Now, test with the fast corner, reduce tOH for the faster RAM, reduce trace board delay ... and might be pretty tight.

And still stable on MiST :)


Nothing compares to a real MiST :)
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Re: Mister SNES port to MIST possible?

Postby slingshot » Sat Nov 23, 2019 9:50 pm

ijor wrote:
1 - This is with the smaller 1.1 shift that works better for them.
2 - This is not the fast corner. This is slow corner at low temp. Yes, you have to check the fastest corner even with the slowest FPGA speed grade.
3 - This is assuming the datasheet is accurate.
4 - You might have overestimated the minimum trace board delay.


I got 2.986 with the Fast model. I leave the rest as a homework for the Mistica guys, it works for me :) It's possible even the PCB traces there are longer/shorter, or have more difference in their length.

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Re: Mister SNES port to MIST possible?

Postby slingshot » Sat Nov 23, 2019 10:22 pm

ijor wrote:
4 - You might have overestimated the minimum trace board delay.


If I calculate of the speed of a PCB trace with c/2, and then looking up various sources on the internet, 20-30mm is about 0.1ns. Even if add it twice to the tOH, it's true - the current value is overestimated heavily. If the tOH in the datasheet is already too high, then it's super-overestimated.


Nothing compares to a real MiST :)

So True :)

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Re: Mister SNES port to MIST possible?

Postby slingshot » Sun Nov 24, 2019 8:58 pm

ManuFerHi wrote:I had not thought Cyclone10, I see that the price does not rise too only about € 10, perhaps it is interesting.

Well, I would vote for a Cyclone10 (more future-proof), and a 64MB SDRAM, but no need for a 160 MHz (-6), 133 MHz is enough (-75) OR -6 speed grade SDRAM, but then a faster FPGA, too (not -8).
+ 3x8 bit video, also available to the outside world (possibility to build an external HDMI scaler)
+ think about a more powerful ARM, at least a faster SPI to the FPGA (loading bigger ROMs takes ages) - Upd: this is mostly limited by the SD-Card specs, in SPI mode there's no high-speed.
Last edited by slingshot on Mon Nov 25, 2019 10:26 am, edited 1 time in total.

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Re: Mister SNES port to MIST possible?

Postby squid4 » Mon Nov 25, 2019 12:31 am

Cyclone 10? So twice the gates and BRAM of the MiST and half of the MiSTer? Should be enough for most retro needs and affordable. SD card, not microSD please. The MIST successor?

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Re: Mister SNES port to MIST possible?

Postby ijor » Mon Nov 25, 2019 3:59 am

ManuFerHi wrote:Yes, i´m use the AS4C16M16SA-6TCN sdram memory. In snes core is estable at -(1000-1500ps) sdram clk phase. Others cores not have this issue.
... with micron memories there is no problem but unfortunately they are no longer manufactured.


The problem here is probably actually that the Alliance chip is too good. We know from the MiSTer experience that it seems to outperform any other brand.

Btw, there is some talk on the MiSTer subforum about possible Alliance counterfeits, may be with lower speed grades re labelled as faster ones. But again, the need of using a smaller phase shift suggests that the problem here is the opposite. They are, apparently, too fast and not too slow.
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Re: Mister SNES port to MIST possible?

Postby slingshot » Mon Nov 25, 2019 8:59 am

squid4 wrote:Cyclone 10? So twice the gates and BRAM of the MiST and half of the MiSTer? Should be enough for most retro needs and affordable. SD card, not microSD please. The MIST successor?

What I saw that FPGA is ~50EUR at Mouser, the Mister's FPGA is more expensive than the DE10nano board itself :) Actually there are more than 3x BRAM. So would be a good upgrade path.

ijor wrote:The problem here is probably actually that the Alliance chip is too good. We know from the MiSTer experience that it seems to outperform any other brand.

I feel it was rather pointless to put such a fast RAM into a clone, and pairing with the slowest speed grade FPGA is not a well-balanced solution. You cannot really write a 160MHz SDRAM controller which will meet timing (probably only a very simple one). That's what's good with the original MiST - all of its components are well-balanced to each other.

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Re: Mister SNES port to MIST possible?

Postby robinsonb5 » Mon Nov 25, 2019 12:38 pm

@ManuFerHi:
Have you tried adjusting drive strength settings on the SDRAM signals?
(I once had trouble on a Xilinx-based board where I just couldn't get the SDRAM to work reliably, reducing the drive strength is what finally fixed it.)

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Re: Mister SNES port to MIST possible?

Postby ManuFerHi » Mon Nov 25, 2019 10:07 pm

robinsonb5 wrote:@ManuFerHi:
Have you tried adjusting drive strength settings on the SDRAM signals?
(I once had trouble on a Xilinx-based board where I just couldn't get the SDRAM to work reliably, reducing the drive strength is what finally fixed it.)

How is drive strength reduced? sorry but I don't know all the quartus options

It affects other parameters, it is not just the model and speedgrade of the sdram.
For example, I changed the clk_sdram pin in SiDi for another. Now the SNES core doesn't work for me at any phase. The only way to make it work has been in phase 0 and with the option in PLL Zero delay mode. Now it is very stable.

Well, I would vote for a Cyclone10 (more future-proof), and a 64MB SDRAM, but no need for a 160 MHz (-6), 133 MHz is enough (-75) OR -6 speed grade SDRAM, but then a faster FPGA, too (not -8).
+ 3x8 bit video, also available to the outside world (possibility to build an external HDMI scaler)
+ think about a more powerful ARM, at least a faster SPI to the FPGA (loading bigger ROMs takes ages) - Upd: this is mostly limited by the SD-Card specs, in SPI mode there's no high-speed.

If you make the scheme and tell me the part numbers of what you want, I make the circuit, perhaps a DAC audio would also be interesting.
On the sdram, my intention was 32mb as standard and a Mister-compatible expansion connector to be able to use the same memory modules and perhaps having two memory buses is good.

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Re: Mister SNES port to MIST possible?

Postby slingshot » Mon Nov 25, 2019 10:34 pm

ManuFerHi wrote:
robinsonb5 wrote:@ManuFerHi:
Have you tried adjusting drive strength settings on the SDRAM signals?
(I once had trouble on a Xilinx-based board where I just couldn't get the SDRAM to work reliably, reducing the drive strength is what finally fixed it.)

How is drive strength reduced? sorry but I don't know all the quartus options

It's the CURRENT_STRENGTH_NEW in the qsf, set it to 4MA.

It affects other parameters, it is not just the model and speedgrade of the sdram.
For example, I changed the clk_sdram pin in SiDi for another. Now the SNES core doesn't work for me at any phase. The only way to make it work has been in phase 0 and with the option in PLL Zero delay mode. Now it is very stable.

Just check if the pin used is a dedicated output of a PLL. Using the dedicated output greatly reduces clock delay. However if the SDRAM doesn't require any phase shift @126 MHz, then it's really fast and connected with 0 clock skew.

If you make the scheme and tell me the part numbers of what you want, I make the circuit, perhaps a DAC audio would also be interesting.
On the sdram, my intention was 32mb as standard and a Mister-compatible expansion connector to be able to use the same memory modules and perhaps having two memory buses is good.


I'm not really an expert designing such hardware, but I think about a 10CL055 FPGA (the cheapest variant is 41 EUR @Mouser) - higher speed grade would be better of course, if it fits the budget.
I don't think it wouldn't make sense to have a 32MB SDRAM now - the controller code for 32MB could be used unchanged, maybe if it does full page burst, then it has to be adjusted, but I'm not aware of any core doing that. External SDRAM would be cool, as two independent module will give tremendous amount of bandwidth. However the external connector should be planned very cleverly to avoid problems with long traces and noise.
The ARM probably doesn't have to be changed - SD card in SPI mode couldn't speeded up more, only 4 wire mode could have higher speeds. But that requires many code changes and re-thinking of the SD-connection.
Of course the usual JTAG, SW12, SAM-BA pins should be there.
And 3x8 bits digital output pins, pixel clock, etc.. - maybe somebody will design a fully digital HDMI scaler for it.
About a better DAC - I'm not an audiophile, and these systems also not high-end audio equipments, thus I don't care.

Well, this would be my next dream single board FPGA, however I don't know if it would attract some more developers, since without them, it's just a paperweight.

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Re: Mister SNES port to MIST possible?

Postby ManuFerHi » Mon Nov 25, 2019 10:53 pm

Just check if the pin used is a dedicated output of a PLL. Using the dedicated output greatly reduces clock delay. However if the SDRAM doesn't require any phase shift @126 MHz, then it's really fast and connected with 0 clock skew.


That's why I made the PIN change, in the first prototype I didn't use a pin dedicated to PLL and in quartus I had warnings. In the final circuit is PLL1 of the 4 there are. The most problematic cores have been SNES and genesis, as I have already said goes very stable in zero delay.
Genesis I had to put the C3 (external clk_sdram) from -0.77ns to 0 (I tried all possible combinations) as it works best is 0, and although the core is functional and many games are going well, some like outrun I have some Glitchs in the car.

What I have not done has been to dedicate 2 pins to the 27mhz clock input, I thought that no core used it, but I think Mistery uses the two inputs and is the only core at the moment that does not work for me (Atari classic core does work perfectly ).

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Re: Mister SNES port to MIST possible?

Postby slingshot » Mon Nov 25, 2019 11:13 pm

ManuFerHi wrote:Genesis I had to put the C3 (external clk_sdram) from -0.77ns to 0 (I tried all possible combinations) as it works best is 0, and although the core is functional and many games are going well, some like outrun I have some Glitchs in the car.

Maybe you can try yesterday's release, it has a new SDRAM controller. With 0 delay of the SDRAM_CLK, the multicycle path in the sdc from SDRAM_CLK->memclk should be removed.

What I have not done has been to dedicate 2 pins to the 27mhz clock input, I thought that no core used it, but I think Mistery uses the two inputs and is the only core at the moment that does not work for me (Atari classic core does work perfectly ).

No, it doesn't use 2 CLOCK27 inputs. Traces of these are probably remains from the first designs.


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