Defender/Robotron/Joust on MiST?

https://github.com/mist-devel/mist-board/wiki

Moderators: Mug UK, Zorro 2, spiny, Greenious, Moderator Team

phoboz
Atariator
Atariator
Posts: 29
Joined: Sun Jan 15, 2017 10:52 pm

Defender/Robotron/Joust on MiST?

Postby phoboz » Wed Dec 05, 2018 11:29 am

Hello,
Has anyone tried to port the Defender Arcade core to MiST?
If this is ported, it should be easy to support Robotron, and Joust also.
https://github.com/MiSTer-devel/Arcade-Defender_MiSTer

I am trying, but I cannot figure out what the different Clock rates shall be?
(I cannot check the pll wizard, as the Project is for Cyclone V, and the version of Quartus II used for MiST will give an several errors when trying to load the Project)

Code: Select all

105  pll pll
106  (
107     .refclk(CLK_50M), //// This one is obvious 50 MHz, for MiST it should be 54 MHz
108     .rst(0),
109     .outclk_0(clk_48), //// 48 MHz?
110     .outclk_1(clk_sys), //// What is this Clock rate?
111     .outclk_2(clk_6p),  //// What is this Clock rate, phase shift etc?
112     .locked(pll_locked)
113  );
114 
 
115  apll apll
116  (
117     .refclk(CLK_50M),
118     .rst(0),
119     .outclk_0(clk_1p79), //// Another Clock I cannot determine the rate of, name makes it hard to guess?
120     .outclk_1(clk_0p89) //// Another Clock I cannot determine the rate of, name makes it hard to guess?
121  );


Also the Project seems to use a lot of block ram on the FPGA, however, it should be possible to use SDRAM for the ROM image at least.

slingshot
Captain Atari
Captain Atari
Posts: 339
Joined: Mon Aug 06, 2018 3:05 pm

Re: Defender/Robotron/Joust on MiST?

Postby slingshot » Wed Dec 05, 2018 11:54 am

You can check it in pll.v, the comment section. As I see, the clocks are: 48, 24, 6MHz, phase shift is 0. Most of the time phase is 0, except for SDRAM clocks.
apll is 1.791044 and 0.895522 MHz.

If you want to use the SDRAM, probably you can use the inverted 48MHz as a clock for it (e.g. SDRAM_CLK <= ~c0)
For a ROM loading to SDRAM example, I suggest you to take a look at the recently updated Colecovision core, it's simple enough.

phoboz
Atariator
Atariator
Posts: 29
Joined: Sun Jan 15, 2017 10:52 pm

Re: Defender/Robotron/Joust on MiST?

Postby phoboz » Thu Dec 06, 2018 12:40 pm

Thank's for the tip.

The core will fit in the FPGA provided that the Program ROM, and the Sound ROM is loaded into SDRAM.

The next problem porting this core is related to that MiST SDRAM address bus has 13-bits, however, the Mister core has 16-bits, and the original core (from Dar) has a 15-bit wide address bus for the on-chip Program ROM memory block (the one that cannot fit in the MiST FPGA)

So I need to find a way to make this work with 13-bit address bus for the MiST.

phoboz
Atariator
Atariator
Posts: 29
Joined: Sun Jan 15, 2017 10:52 pm

Re: Defender/Robotron/Joust on MiST?

Postby phoboz » Thu Dec 06, 2018 1:55 pm

Please forgive me for aksing perhaps really basic questions on the MiST SDRAM, but; I want to access 32 KByte of data mapped as below with just 13-bits, how can I achive this?

Code: Select all

-- should reflect content of defender_prog.bin
--
-- 4k 0000-0FFF  cpu_space D000-DFFF defend.1 + defend.4 
-- 4k 1000-1FFF            E000-EFFF defend.2
-- 4k 2000-2FFF            F000-FFFF defend.3
-- 4k 3000-3FFF  page=1    C000-CFFF defend.9 + defend.12
-- 4k 4000-4FFF  page=2    C000-CFFF defend.8 + defend.11
-- 4k 5000-5FFF  page=3    C000-CFFF defend.7 + defend.10
-- 4k 6000-6FFF  page=7    C000-C7FF defend.6 + 2k empty
-- 4k 7000-7FFF            N.A       4k empty

slingshot
Captain Atari
Captain Atari
Posts: 339
Joined: Mon Aug 06, 2018 3:05 pm

Re: Defender/Robotron/Joust on MiST?

Postby slingshot » Thu Dec 06, 2018 2:40 pm

phoboz wrote:Thank's for the tip.

The core will fit in the FPGA provided that the Program ROM, and the Sound ROM is loaded into SDRAM.

The next problem porting this core is related to that MiST SDRAM address bus has 13-bits, however, the Mister core has 16-bits, and the original core (from Dar) has a 15-bit wide address bus for the on-chip Program ROM memory block (the one that cannot fit in the MiST FPGA)

So I need to find a way to make this work with 13-bit address bus for the MiST.


The physical address bus of the SDRAM is not the same as addressing the full capacity of it (because it has the necessary width for the row address). You should use the SDRAM controller, which gives you plenty of address space, like the one I used in Colecovision for example (Master of Gizmo and Sorgelig have written more than enough SDRAM controllers):
https://github.com/wsoltys/mist-cores/b ... t/sdram.sv
There addr is 25 bits wide, more than enough.
Just give it a clock of at least 8x the CPU clock, and then it's almost the same as using BRAM.


Return to “MiST”

Who is online

Users browsing this forum: No registered users and 8 guests