Search found 3031 matches

by ijor
Wed Dec 18, 2019 12:48 pm
Forum: 680x0
Topic: Understanding the Union Demo's Opening of left and right borders
Replies: 37
Views: 4483

Re: Understanding the Union Demo's Opening of left and right borders

the table lists the times at which tests occur on CPU-accessible state. I'm not sure I understand the meaning of " on CPU-accessible state " in this context. I'm not sure it is needed. It does not specify the times at which actions will occur as a result. Further, where it lists two resul...
by ijor
Tue Dec 17, 2019 6:21 pm
Forum: 680x0
Topic: Understanding the Union Demo's Opening of left and right borders
Replies: 37
Views: 4483

Re: Understanding the Union Demo's Opening of left and right borders

Okay, so then I think I will plan to edit the Wiki to make it explicit that the timings in that table are given only to a four-cycle precision and may show some inaccurate aliasing* — i.e. they're those that are observable from the CPU** and that's all. No. I don't think that is an accurate descrip...
by ijor
Tue Dec 17, 2019 12:19 pm
Forum: 680x0
Topic: Understanding the Union Demo's Opening of left and right borders
Replies: 37
Views: 4483

Re: Understanding the Union Demo's Opening of left and right borders

I don't think the Wiki takes a clear position on what it's documenting, and if anything implies itself to be a hardware documentation: It might be not clear, but I know from talks with Troed what's exactly the meaning of that table. Furthermore, the whole philosophy of the article is, obviously, fr...
by ijor
Mon Dec 16, 2019 7:42 pm
Forum: 680x0
Topic: Understanding the Union Demo's Opening of left and right borders
Replies: 37
Views: 4483

Re: Understanding the Union Demo's Opening of left and right borders

I had made some edits to that wiki page for readability even before starting this thread; I'll try to fold what I've learnt back in. I mean, those HSYNC times look wrong because they'd result in only 458 cycles of DE active, which doesn't seem to give the 115 word fetches that are not only definite...
by ijor
Mon Dec 16, 2019 3:40 am
Forum: MiST
Topic: It's no more a MiSTery
Replies: 310
Views: 46228

Re: It's no more a MiSTery

As the mouse is a rotary encoder, it constantly turns on-off it's outputs as you move it in a Gray-coded scheme. Now it's possible when you stop it, it's left in a postion where some pins are high, some are low. No problem. ... I really wonder what state an original Atari mouse leaves its outputs w...
by ijor
Sat Dec 14, 2019 10:13 pm
Forum: 680x0
Topic: Understanding the Union Demo's Opening of left and right borders
Replies: 37
Views: 4483

Re: Understanding the Union Demo's Opening of left and right borders

Again, I might be relying too much on the wiki as hardware documentation rather than an observed-from-the-CPU documentation, but it has the blank level never being activated by the loop as from that demo — it’s in 72Hz mode as the raster crosses that test ... I thought it used the other style of st...
by ijor
Sat Dec 14, 2019 1:36 am
Forum: 680x0
Topic: Understanding the Union Demo's Opening of left and right borders
Replies: 37
Views: 4483

Re: Understanding the Union Demo's Opening of left and right borders

But I guess what’s happening here is that the final pixels are obscured by the sync level, and after that output is in 72Hz mode, so the border colour is the blank level, and by the time 50Hz is reestablished the retrace is over. Blanking is only indirectly related to sync. The hardware performs bl...
by ijor
Fri Dec 13, 2019 8:58 pm
Forum: 680x0
Topic: Understanding the Union Demo's Opening of left and right borders
Replies: 37
Views: 4483

Re: Understanding the Union Demo's Opening of left and right borders

If DE remains active 460 cycles, running right up against HSYNC, even if you ignore the latency in LOAD relative to DE, why does that not result in pixels being output during the blanking period? Shifter, or DE for that matter, has nothing to do with blanking. Even on a normal non fullscreen, Shift...
by ijor
Thu Dec 12, 2019 11:54 pm
Forum: 680x0
Topic: Understanding the Union Demo's Opening of left and right borders
Replies: 37
Views: 4483

Re: Understanding the Union Demo's Opening of left and right borders

I didn't infer DE timing from the switch timing. The wiki lists the relevant events as: ⋅  cycle 4: IF(71) H = TRUE ⋅  LINE-50: IF(!71) HSYNC = TRUE && H = FALSE LINE is 512. So LINE-50 = 462. I can't comment too much on the wiki rationale. It is written from a programme...
by ijor
Thu Dec 12, 2019 1:35 am
Forum: FPGA Chat
Topic: How long will they last?
Replies: 7
Views: 2548

Re: How long will they last?

This is quite reassuring. I was hoping for my MiST and MiSTer to last a good long time. I could not find any documentation on the mtbf on FPGAs. There is a reliability report at Intel for the Altera Cyclone V SE FPGA (which I just found) which lists the FIT as 13.5. I'm not sure those figures make ...
by ijor
Thu Dec 12, 2019 1:30 am
Forum: 680x0
Topic: Understanding the Union Demo's Opening of left and right borders
Replies: 37
Views: 4483

Re: Understanding the Union Demo's Opening of left and right borders

At a "normal" fullscreen, like the Level 16 screen at Union Demo, DE is active for 460 cycles, not 458. You can't infer the exact DE timing from the switches timing. It doesn't work like that. A switch doesn't provoke a DE edge immediately. It just puts GLUE on a state that it will trigger...
by ijor
Thu Dec 12, 2019 1:21 am
Forum: MiSTer
Topic: USB Floppy support on MiSTer? Possible? Needed?
Replies: 15
Views: 2571

Re: USB Floppy support on MiSTer? Possible? Needed?

Wouldn't it make a lot more sense to just run the floppy drive control signals out to the GPIO header and attach a standard mechanism? Or are the cores "cheating" and not fully implementing the drive controllers in the first place? Yes, I believe most cores do "cheat". Although ...
by ijor
Thu Dec 12, 2019 1:17 am
Forum: MiSTer
Topic: MiSTery Atari ST/STe core
Replies: 21
Views: 6717

Re: MiSTery Atari ST/STe core

I will port the core. Just need to find the time. Hopefully shortly :)
by ijor
Thu Dec 12, 2019 1:15 am
Forum: MiSTer
Topic: FX CAST Atari ST core
Replies: 309
Views: 128174

Re: FX CAST Atari ST core

Any chance for atari ste? Yes, it is planned. But it is not at the top of the list :) I haven't experienced the situation where the controllers stop working in any other core but this one. I would think if it was framework-related, it would also appear in other cores. Just my experience, thanks for...
by ijor
Tue Dec 03, 2019 12:54 am
Forum: MiSTer
Topic: USB Floppy support on MiSTer? Possible? Needed?
Replies: 15
Views: 2571

Re: USB Floppy support on MiSTer? Possible? Needed?

A connection method for a real floppy could be done via already mentioned projects like Supercard Pro, KryoFlux, FluxEngine, Greaseweazel or SlamySTM32Floppy via USB. It would "just" need some drivers on the MiSTer side, but this is not easy - ideally, you'd want to translate the simulate...
by ijor
Tue Dec 03, 2019 12:23 am
Forum: Hardware
Topic: Greaseweazle disk image reader writer
Replies: 17
Views: 3361

Re: Greaseweazle disk image reader writer

I'm not talking about the power supply, but about the maximum current of the input/output buffers/drivers at the board. Older DD 5.25 drives (not just any 5.25 drive) require high current components. Now I understand. Are there risks to the hardware if the buffers don’t get enough current? Probably...
by ijor
Tue Dec 03, 2019 12:20 am
Forum: MiST
Topic: It's no more a MiSTery
Replies: 310
Views: 46228

Re: It's no more a MiSTery

slingshot wrote:I've introduced a bug in MFP, because I used a buggy datasheet (heh, wrong datasheets are floating around).


What buggy MFP datasheet are (were) you using ???
by ijor
Tue Dec 03, 2019 12:18 am
Forum: FPGA Chat
Topic: How long will they last?
Replies: 7
Views: 2548

Re: How long will they last?

How long is an FPGA system likely to last? With the constant reprogramming and regular usage, how long before those gates and latches tightly integrated into that massive chip begin to break down? It occurs to me that FPGAs were originally developed to model and design circuits and systems for prod...
by ijor
Sat Nov 30, 2019 12:30 pm
Forum: Hardware
Topic: Greaseweazle disk image reader writer
Replies: 17
Views: 3361

Re: Greaseweazle disk image reader writer

Bama wrote:Yes the 5 1/4 drives must have an external power supply.


I'm not talking about the power supply, but about the maximum current of the input/output buffers/drivers at the board. Older DD 5.25 drives (not just any 5.25 drive) require high current components.
by ijor
Sat Nov 30, 2019 11:47 am
Forum: 680x0
Topic: The secrets of the 68000
Replies: 21
Views: 3439

Re: The secrets of the 68000

I edited the post with the article about the I/N field. One section was expanded because I was told it was difficult to understand. The attached PDF article was also updated accordingly. There are currently also some other differences in exception handling when comparing real HW with emulation, for ...
by ijor
Thu Nov 28, 2019 7:14 pm
Forum: Hardware
Topic: Greaseweazle disk image reader writer
Replies: 17
Views: 3361

Re: Greaseweazle disk image reader writer

Btw, it is just by chance that the name is so similar to the Catweasel, a predecessor of all these "flux level" devices?
by ijor
Thu Nov 28, 2019 7:09 pm
Forum: Hardware
Topic: Greaseweazle disk image reader writer
Replies: 17
Views: 3361

Re: Greaseweazle disk image reader writer

It is very nice to have an open source alternative to SCP and the Kryoflux. But unless somebody will provide this fully assembled, and with software that would run directly without something like phyton, then it would be very restricted. Btw, I'm not sure this device is suitable for older 5.25 drive...
by ijor
Wed Nov 27, 2019 1:02 am
Forum: 680x0
Topic: The secrets of the 68000
Replies: 21
Views: 3439

Re: The secrets of the 68000

I guess no emulator handles this correctly? Not that I know. But I'm in contact with Toni Wilen (Winuae maintainer) and already let him know. Well, what is "correctly"? If i understand that, it could also happen that an interrupt happens as the "next" instruction, which would ha...
by ijor
Tue Nov 26, 2019 1:18 pm
Forum: 680x0
Topic: The secrets of the 68000
Replies: 21
Views: 3439

Re: The I/N field on the bus and address error stack frame

Attached in a small article I wrote about the bus and address exception stack frame. Whole article in PDF form (updated version): M68000-ExceptionStackFrame.pdf I am pasting here the sections relevant to the I/N field. But it might be easier to understand the context checking the whole article. ...,...
by ijor
Tue Nov 26, 2019 1:09 pm
Forum: MiST
Topic: Mister SNES port to MIST possible?
Replies: 279
Views: 40750

Re: Mister SNES port to MIST possible?

AFAIK the skew created by the zero delay mode affects all off the clock networks. Aligning and compensating are two different things. All internal clocks are aligned, unless explicitly shifted, and don't require compensation. But the external output is not aligned with the internal ones and might h...

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