Search found 2703 matches

by ijor
Wed Nov 14, 2018 9:25 pm
Forum: MiST
Topic: Genesis / Megadrive core ported to MiST
Replies: 769
Views: 81965

Re: Genesis / Megadrive core ported to MiST

Surely the DDR bandwidth is more than enough. The problem might be the latency. The hardware interface (MPFE) is extremely efficient and the latency is much lower than I expected. But is not fully predictable because you don't control the hardware directly as you do with the SDRAM. Is the ROM access...
by ijor
Wed Nov 14, 2018 8:53 pm
Forum: News & Announcements
Topic: FX68K Cycle accurate 68000 core
Replies: 22
Views: 897

Re: FX68K Cycle accurate 68000 core

fpgaarcade wrote:note, I modified the top to bring out the PHI enables directly. I had to use a different synthesis tool as the old Xilinx software does not support SV


Hi Mike. Please check the download as it is slightly modified in relation to what you had. I'm not using a struct as an external port anymore.
by ijor
Wed Nov 14, 2018 8:52 pm
Forum: News & Announcements
Topic: FX68K Cycle accurate 68000 core
Replies: 22
Views: 897

Re: FX68K Cycle accurate 68000 core

https://i.imgur.com/rGp7wq6.png This is where it gets to with asserting PHI1 on 0 and PHI2 on 4 (with a 3-bit clock divider). Not sure if that's what you want, but seems you are dividing the clock by 8. I see 8 cycles between each PHI1 pulses. I also see that DTACK is deasserted too late, well when...
by ijor
Wed Nov 14, 2018 8:28 pm
Forum: News & Announcements
Topic: FX68K Cycle accurate 68000 core
Replies: 22
Views: 897

Re: FX68K Cycle accurate 68000 core

I am probably stating the obvious, but if you are migrating from TG68K (as I guess you are), you must take are of all the details of the 68000 bus interface that TG68K simplifies. Most signals are not active during the whole bus cycle, but only on specific cycles and phases. And the processor expec...
by ijor
Wed Nov 14, 2018 5:28 pm
Forum: News & Announcements
Topic: FX68K Cycle accurate 68000 core
Replies: 22
Views: 897

Re: FX68K Cycle accurate 68000 core

Out of pure curiosity, how long did it take you to complete it? Well, it depends on when you consider I really started :) ... I started research and reverse engineering of the 68000 many years ago. I decrypted (so to speak, they are not encrypted, but they are barely readable) the patents, and stud...
by ijor
Wed Nov 14, 2018 5:19 pm
Forum: News & Announcements
Topic: FX68K Cycle accurate 68000 core
Replies: 22
Views: 897

Re: FX68K Cycle accurate 68000 core

How close together can the PHI1 and PHI2 pulses be? Can they just be asserted on each alternate clk edge? Any reason why those can't be generated within the FX68K core itself? I mean, it's not a huge deal, but would it be possible to have only the original 68000 signals exposed? (I see there's a no...
by ijor
Wed Nov 14, 2018 5:05 pm
Forum: News & Announcements
Topic: FX68K Cycle accurate 68000 core
Replies: 22
Views: 897

Re: FX68K Cycle accurate 68000 core

can you release it on github? Then there will be a central development repo for this IP, so you can get some pull requests if you don't mind. Sure, no problem. But give me please a couple of days. Should reset be released before specific enPhi1/2 or doesn't matter? Shouldn't matter. I am probably s...
by ijor
Wed Nov 14, 2018 1:39 pm
Forum: MiSTer
Topic: FX CAST Atari ST core
Replies: 76
Views: 6604

Re: FX CAST Atari ST core

Portable sources for the 68000 core has been released: viewtopic.php?f=28&t=34730
by ijor
Wed Nov 14, 2018 12:31 pm
Forum: MiST
Topic: Genesis / Megadrive core ported to MiST
Replies: 769
Views: 81965

Re: Genesis / Megadrive core ported to MiST

Gehstock wrote:For the Roms


Just out of curiosity, which bandwidth requires the ROM? Access needs to be cycle accurate? Otherwise, the DDR can be used, may be using some internal cache in the worst case. I was surprised to find out how efficient the DDR access from the FPGA side is.
by ijor
Wed Nov 14, 2018 11:56 am
Forum: FPGA Chat
Topic: Alternative to GPL license
Replies: 16
Views: 512

Re: Alternative to GPL license

I finally released the source under the GPL license: viewtopic.php?f=28&t=34730

I decided it wasn't worth the complication to write a special license or use a more restricted one.
by ijor
Wed Nov 14, 2018 11:53 am
Forum: News & Announcements
Topic: FX68K Cycle accurate 68000 core
Replies: 22
Views: 897

Re: FX68K Cycle accurate 68000 core

SystemVerilog sources:

http://fx68k.fxatari.com/fx68k-Source.zip

FX68K is released under the GPL open source license.
More material including notes, tables and charts, that I need yet to finish or polish, should be available at some later time.
by ijor
Wed Nov 14, 2018 11:50 am
Forum: News & Announcements
Topic: FX68K Cycle accurate 68000 core
Replies: 22
Views: 897

FX68K Cycle accurate 68000 core

FX68K Copyright (c) 2018 by Jorge Cwik fx68k@fxatari.com FX68K is a 68000 cycle exact compatible core. At least in theory, it should be impossible to distinguish functionally from a real 68K processor. On Cyclone families it uses just over 5,100 LEs and about 5KB internal ram, reaching a max effect...
by ijor
Tue Nov 13, 2018 9:11 pm
Forum: FPGA Chat
Topic: Alternative to GPL license
Replies: 16
Views: 512

Re: Alternative to GPL license

As for me, I think the purpose of an open source license about retro stuff should be to promote more work done in the scene. So a license that requires publishing the core source is a must. I agree of course. To be honest, I'm afraid that the license has a limited protection in cases like this. The...
by ijor
Tue Nov 13, 2018 3:18 pm
Forum: FPGA Chat
Topic: Alternative to GPL license
Replies: 16
Views: 512

Re: Alternative to GPL license

So i don't see much contradict here. It's like endless patents war between Apple and Samsung. They don't have rights to devices of each other while they still sue each other for infringements of specific rights. You don't have right for produced device based on your HDL, but still (in theory) can s...
by ijor
Tue Nov 13, 2018 2:00 pm
Forum: FPGA Chat
Topic: Alternative to GPL license
Replies: 16
Views: 512

Re: Alternative to GPL license

And where you've got that HDL is not protected as software? Strictly speaking HDL is the same source code compiled to binary the same way as traditional software for barebone MCU. Will this binary used as microcode for CPU or connect the logic in configurable array - it's already doesn't matter. Op...
by ijor
Tue Nov 13, 2018 12:59 pm
Forum: FPGA Chat
Topic: Alternative to GPL license
Replies: 16
Views: 512

Re: Alternative to GPL license

I think the closest you can come is to use Creative Commons NC (non-commercial) SA (share-alike). After that you indicate on your website that hobbyists can contact you for a commercial license (you write to them that it's ok in an email). Yes, I know I can use this strategy. But this is not really...
by ijor
Tue Nov 13, 2018 2:19 am
Forum: MiSTer
Topic: Scaler
Replies: 89
Views: 5952

Re: Scaler

- The low latency mode synchronizes the display of the first line of the output image with the third line of the input image, by delaying the vertical sync. pulse. I don't know if it works on an actual TV. Any change on the sync timing would make some ill effects on most monitors. But as long as it...
by ijor
Tue Nov 13, 2018 12:52 am
Forum: FPGA Chat
Topic: Alternative to GPL license
Replies: 16
Views: 512

Alternative to GPL license

I am ready to release the sources of my 68000 cycle accurate core. I just need to decide which open source license to use. I admit I am not precisely a GPL fan. And I would like to hear comments about other possible alternatives. My main concern, or at least my main doubts, are about allow commercia...
by ijor
Fri Nov 09, 2018 12:27 pm
Forum: MiSTer
Topic: DE-10 Super Expansion board
Replies: 10
Views: 1106

Re: DE-10 Super Expansion board

Sorgelig wrote:DB9 connected to FPGA won't provide the same flexibility as USB ...


Absolutely. Nobody said it would replace USB controllers. It just would be an alternative.
by ijor
Fri Nov 09, 2018 10:57 am
Forum: MiSTer
Topic: DE-10 Super Expansion board
Replies: 10
Views: 1106

Re: DE-10 Super Expansion board

I am working on finalizing a board for the DE-10 that gives you the basic features of the MiSTer I/O board, SDRAM board, and RTC board - all in a single plug-in board. A unified single board is great! As mentioned in other thread, I had the idea to add a DB-9 connector for old school joysticks, may...
by ijor
Thu Nov 08, 2018 2:01 pm
Forum: MiSTer
Topic: MiSTer + OSSC
Replies: 16
Views: 1403

Re: MiSTer + OSSC

I used a scope with a Mc Cthulu arcade board to the mister. For testing, the genesis core was modified to light the user LED when it received input. One probe was on the button itself, the other probe on the user LED. Counting only tests that had low bounce, the average latency I saw on the scope b...
by ijor
Thu Nov 08, 2018 12:06 pm
Forum: MiSTer
Topic: MiSTer + OSSC
Replies: 16
Views: 1403

Re: MiSTer + OSSC

Besides the scaler, is there anything that can be done to further reduce the lag? Increase the USB polling interval perhaps? I wonder how much lag we get from the controllers. Somebody performed any measurements as that guy did with the HDMI video output lag? If the lag is significant, and probably...
by ijor
Wed Nov 07, 2018 4:59 pm
Forum: MiSTer
Topic: Scaler
Replies: 89
Views: 5952

Re: Scaler

And even this wait signal for scaler is not required, as video module of emulation system may watch the output sync and hold itself till the right time. If reading and writing speeds are the same, then it should be done only once at core start. Yes, it is possible. But seems to me kinda a retorted ...
by ijor
Wed Nov 07, 2018 12:53 pm
Forum: MiSTer
Topic: Scaler
Replies: 89
Views: 5952

Re: Scaler

I repeat, there is nothing should be changed in scaler - everything is there already. Lag depends on difference between writing to buffer and reading form it. With triple frame buffering, you start reading from a buffer that was already completely written. You never read and write to the same buffe...
by ijor
Wed Nov 07, 2018 11:43 am
Forum: MiSTer
Topic: Scaler
Replies: 89
Views: 5952

Re: Scaler

And for this reason it might be worth to have the scaler ready to operate with the shortest possible lag. I didn't contradict it. Where i've said i'm against it? I've just wrote that in general case it doesn't depend on scaler. Scaler only needs one signal "wait" to hold on vsync start (a...

Go to advanced search