Search found 2904 matches

by ijor
Sat Aug 17, 2019 4:07 pm
Forum: Coding
Topic: Timer B + DMA at once
Replies: 17
Views: 445

Re: Timer B + DMA at once

I'm not familiar with the Falcon, but AFAIK the Shifter (or Videl) can steal cycles from the CPU there. No idea with the Falcon/Videl either, but Shifter doesn't steal any CPU cycles. It is MMU which might steal CPU cycles if the CPU attempt a bus access at a slot that it's not its own. But this MM...
by ijor
Sat Aug 17, 2019 3:52 pm
Forum: Coding
Topic: Timer B + DMA at once
Replies: 17
Views: 445

Re: Timer B + DMA at once

STe sound DMA (as opposed to Blitter DMA, or to ACSI DMA) is completely transparent and non intrusive. It works the same as screen Shifter DMA. It doesn't affect and doesn't steal any CPU cycles at all.
by ijor
Sat Aug 17, 2019 11:28 am
Forum: Hardware
Topic: STe - Bad DMA Chip
Replies: 172
Views: 37638

Re: STe - Bad DMA Chip

This was the Atari ST 32768 Colour Showdown. Some pictures aren't displayed correctly with an hcmos 68k. ... Got the time to test the demo again : Same motherboard, Same power supply, Same DRAM, and same room temperature ! ;) Tried to change the PSU, DRAM, place the shield : The issue still there w...
by ijor
Thu Aug 15, 2019 11:00 am
Forum: Coding
Topic: ST Chipset decap
Replies: 144
Views: 53487

Re: ST Chipset decap

npomarede wrote:Yes, on the tests I made on my STF some time ago, I noted that the demo worked in WS1,WS2 an WS4 but gave the vertical black bands in WS3 (WSx names are those from Troed's program to detect WS)


I don't think it's about GLUE-MMU wake states, it depends on the Shifter wakeup.
by ijor
Wed Aug 14, 2019 12:19 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 144
Views: 53487

Re: ST Chipset decap

Death of the left border I was wrong with my previous comment, never trust your memory when you can check on the real HW :) I just connected my old STE on my TV this morning and the demo is indeed working, no stabilization issue, overscan is correct (only on the left part of the 1st overscan line o...
by ijor
Wed Aug 14, 2019 12:18 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 144
Views: 53487

Re: ST Chipset decap

However this reload after 4 load thing causes an interesting issue with STe hard scroll. STe in mono and mid modes is fetching 1 or 2 extra words at the beginning of the line, so it should do something with those extras at the line end, otherwise the next line will break (and the STe test cartridge...
by ijor
Tue Jul 30, 2019 8:57 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 144
Views: 53487

Re: ST Chipset decap

Hi, I'm currently on a trip, at this time I can't really check anything. I will only reply and comment about the global concepts for the time being ... Meanwhile I also implemented a Shifter based on this great information. However I struggle at one point: Death of the left border. Inside the MMU/GL...
by ijor
Wed Jul 17, 2019 2:00 am
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 8763

Re: RAM write wait states

2. DTACK_N asserted at the CPU RAM cycle, at +3 (not too early?) (in the previous - working - core, DTACK_N is not asserted until the incoming data is stable, that's a main difference I guess). Yes, MMU asserts DTACK before ram is actually ready, and that is the correct behavior. According to the 6...
by ijor
Sat Jun 29, 2019 1:20 pm
Forum: Hardware
Topic: ST TOS ROMs - what is the speed of stock ROMs
Replies: 16
Views: 1860

Re: ST TOS ROMs - what is the speed of stock ROMs

In theory, you need 200ns for the worst case, but in practice, I guess 250ns would probably work. The CPU read cycle is two and a half clock cycles (CPU latches at the S7 falling edge, not at S6). At the slightly faster than 8MHz ST frequency, that would be 310ns. But there are some delays that have...
by ijor
Wed May 08, 2019 2:16 pm
Forum: MiSTer
Topic: FX CAST Atari ST core
Replies: 215
Views: 62748

Re: FX CAST Atari ST core

I did report (http://www.atari-forum.com/viewtopic.php?f=123&t=34496#p355872) that the only messages I saw were concerning the visibility status of the OSD and nothing about button press events - like I did see with the initial version of FX CAST. At that time I was using the physical USB seria...
by ijor
Wed May 08, 2019 1:20 am
Forum: 680x0
Topic: YACHT, MULU # and an extra program fetch
Replies: 10
Views: 2560

Re: YACHT, MULU # and an extra program fetch

First thank you for your interest in these little piece of doc Yacht was (and still is ?). Hi danorf, good do see you here, it is always nice to get answers from the source :) As I said, I wasn't aware about Yatch until rather recently, long after I studied the patent. It would have saved me some t...
by ijor
Wed May 08, 2019 1:07 am
Forum: MiSTer
Topic: FX CAST Atari ST core
Replies: 215
Views: 62748

Re: FX CAST Atari ST core

For what it's worth, I had the joystick input freeze on me twice tonight in the space of a few minutes (It's the first time I've attempted to play a game in FXcast in a while). In this particular instance I was playing Bubble Bobble, but I don't think the problem had anything to do with that. I've ...
by ijor
Mon Apr 29, 2019 5:35 pm
Forum: MiSTer
Topic: Z80, 6502, 6809 ICE Debuging.
Replies: 3
Views: 929

Re: Z80, 6502, 6809 ICE Debuging.

Very interesting. I was always fascinated by hardware debuggers. Back at the day I dreamed with the possibility of having a true 68000 or x86 Ice that was impossible to afford. I planned to implement an ICE interface on my 68K core and some minimal hooks are already there. Nowadays it is usually mor...
by ijor
Mon Apr 29, 2019 5:25 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 8763

Re: RAM write wait states

I'm currently struggling with the clock generators: expected waveforms are at the end of ST4081S.PDF. ... Actually I don't understand the purpose of the second gating latch. The flip-flop latch combination is probably an attempt to reduce clock skew. Not sure how well this actually works in practic...
by ijor
Fri Apr 26, 2019 3:06 pm
Forum: Hardware
Topic: MegaSTE floppy cable - twisted or straight?
Replies: 4
Views: 954

Re: MegaSTE floppy cable - twisted or straight?

Note that the term twisting, in this context, is a little ambiguous. One thing is a cable with some wires twisted. Another thing is a cable that is connected wholly twisted. The former is usually for connecting multiple drives on a PC. The twisted wires changes the drive selection on specific drives...
by ijor
Thu Apr 25, 2019 7:10 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 8763

Re: RAM write wait states

Another question about hardware scroll: on STE, DE always activated 16 pixels earlier? Because on the 4081S schematic, if the scroll register set to 0, then it's delayed by 4 cycles (=16 pixels), so it'll be 80 cycles long, as supposed to be on the original ST. If scroll != 0, then DE starts 4 cycl...
by ijor
Wed Apr 24, 2019 3:54 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 8763

Re: RAM write wait states

... those tons negations always confuse my mind). Not only yours :) Another strangeness (at least for me) - vsync length is only 1 line in mono mode? (in color it's 3 lines, which is perfect). Yes, that's correct. Btw, I forgot to mention, although you probably already figured out it by yourself. T...
by ijor
Wed Apr 24, 2019 1:21 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 8763

Re: RAM write wait states

Progressed a bit with my simulation. I wonder why at https://temlib.org/AtariForumWiki/index.php/ST_STE_Scanlines#Horizontal_GLUE_state_machine.2C_ST says 184 IF(71) BLANK = TRUE but no BLANK reset. In my sim, BLANK reset (or set if I think about BLANK is negated) always active, and set is never ac...
by ijor
Fri Apr 19, 2019 1:10 am
Forum: 680x0
Topic: YACHT, MULU # and an extra program fetch
Replies: 10
Views: 2560

Re: YACHT, MULU # and an extra program fetch

It's a bit of a weird document all around to be honest; it is primarily about what you'd observe on a bus, but slightly overlapping into what's going on inside the 68000. If you're interested in 68000 internals then there's quite a lot of deduction involved. Bus timing and order is important for se...
by ijor
Thu Apr 18, 2019 12:24 pm
Forum: 680x0
Topic: YACHT, MULU # and an extra program fetch
Replies: 10
Views: 2560

Re: YACHT, MULU # and an extra program fetch

Thanks for clearing that up; I've noticed that the document is self-contradictory about TRAP also, so am now doubly disabused of any belief in its perfection. Luckily the proper execution of TRAPs has already been covered here. MULU mistake is probably just a typo. I didn't check Yacht 's TRAP sect...
by ijor
Thu Apr 18, 2019 2:44 am
Forum: MiST
Topic: Any chance of 512kb and 1mb support on the ST core?
Replies: 3
Views: 1785

Re: Any chance of 512kb and 1mb support on the ST core?

There is a little program that changes the memory configuration to 512K RAM. This should fix most, if not all, programs that don't run, or don't run correctly with 4MB RAM. The program should be here somewhere. Don't remember if it was called RAM512K.TOS or something like that. Somebody else probabl...
by ijor
Thu Apr 18, 2019 2:34 am
Forum: 680x0
Topic: Wakestate question
Replies: 1
Views: 1169

Re: Wakestate question

I don't understand exactly what you are doing. If your code depends on the wakeup it means that your timing is wrong. But can't be more precise without more info.

Post your code please. Ideally an executable, for testing quickly, and also your source code, or at least the relevant parts of it.
by ijor
Thu Apr 18, 2019 2:28 am
Forum: 680x0
Topic: YACHT, MULU # and an extra program fetch
Replies: 10
Views: 2560

Re: YACHT, MULU # and an extra program fetch

Yacht is wrong. There is no third prefetch cycle.
by ijor
Mon Apr 15, 2019 12:57 am
Forum: News & Announcements
Topic: Atari800 4.1.0 for Falcon and clones released (update!)
Replies: 20
Views: 6625

Re: Atari800 4.1.0 for Falcon and clones released

I don't have a Falcon myself. But this is certainly an awesome achievement. Congratulations.
by ijor
Sat Apr 13, 2019 1:58 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 8763

Re: RAM write wait states

Also interesting: Dated between "4081.ORG" and "4081" there is the data in the "TXL" folder, also containing a GSTMCU design. The simulation for this references a SCX6B library. SCX6 was a family of gate arrays by National Semiconductor. Also, the numbers next to compo...

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