Search found 2886 matches

by ijor
Fri Apr 19, 2019 1:10 am
Forum: 680x0
Topic: YACHT, MULU # and an extra program fetch
Replies: 8
Views: 747

Re: YACHT, MULU # and an extra program fetch

It's a bit of a weird document all around to be honest; it is primarily about what you'd observe on a bus, but slightly overlapping into what's going on inside the 68000. If you're interested in 68000 internals then there's quite a lot of deduction involved. Bus timing and order is important for se...
by ijor
Thu Apr 18, 2019 12:24 pm
Forum: 680x0
Topic: YACHT, MULU # and an extra program fetch
Replies: 8
Views: 747

Re: YACHT, MULU # and an extra program fetch

Thanks for clearing that up; I've noticed that the document is self-contradictory about TRAP also, so am now doubly disabused of any belief in its perfection. Luckily the proper execution of TRAPs has already been covered here. MULU mistake is probably just a typo. I didn't check Yacht 's TRAP sect...
by ijor
Thu Apr 18, 2019 2:44 am
Forum: MiST
Topic: Any chance of 512kb and 1mb support on the ST core?
Replies: 3
Views: 413

Re: Any chance of 512kb and 1mb support on the ST core?

There is a little program that changes the memory configuration to 512K RAM. This should fix most, if not all, programs that don't run, or don't run correctly with 4MB RAM. The program should be here somewhere. Don't remember if it was called RAM512K.TOS or something like that. Somebody else probabl...
by ijor
Thu Apr 18, 2019 2:34 am
Forum: 680x0
Topic: Wakestate question
Replies: 1
Views: 367

Re: Wakestate question

I don't understand exactly what you are doing. If your code depends on the wakeup it means that your timing is wrong. But can't be more precise without more info.

Post your code please. Ideally an executable, for testing quickly, and also your source code, or at least the relevant parts of it.
by ijor
Thu Apr 18, 2019 2:28 am
Forum: 680x0
Topic: YACHT, MULU # and an extra program fetch
Replies: 8
Views: 747

Re: YACHT, MULU # and an extra program fetch

Yacht is wrong. There is no third prefetch cycle.
by ijor
Mon Apr 15, 2019 12:57 am
Forum: News & Announcements
Topic: Atari800 4.1.0 for Falcon and clones released (update!)
Replies: 20
Views: 1488

Re: Atari800 4.1.0 for Falcon and clones released

I don't have a Falcon myself. But this is certainly an awesome achievement. Congratulations.
by ijor
Sat Apr 13, 2019 1:58 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 36
Views: 2176

Re: RAM write wait states

Also interesting: Dated between "4081.ORG" and "4081" there is the data in the "TXL" folder, also containing a GSTMCU design. The simulation for this references a SCX6B library. SCX6 was a family of gate arrays by National Semiconductor. Also, the numbers next to compo...
by ijor
Wed Apr 10, 2019 5:29 pm
Forum: MiSTer
Topic: FX CAST Atari ST core
Replies: 195
Views: 41934

Re: FX CAST Atari ST core

Iam really glad to see again some activity from Ijor. I've been waiting for 6 month to finally be able to have a look at the HDL. I bet I can wait a little more... ;-) You are welcome to ask as much as you like, but I'll release the source when I'll be ready :) (Also, the current state of FX Cast i...
by ijor
Wed Apr 10, 2019 2:45 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 36
Views: 2176

Re: RAM write wait states

I've made an experiment when the load is async (the load delay flip-flop at the end of the counter chain is unchanged): the difference is that after overflow, it doesn't reset to 0, but the first value will repeat twice. So the number of steps are not changed. If that's the behaviour then everythin...
by ijor
Wed Apr 10, 2019 12:26 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 36
Views: 2176

Re: RAM write wait states

I don't see a flip-flop in LT2, just that one latch. The whole LT2 cell works like a flip-flop. Or you mean that there is no flip-flop INSIDE LT2? If so, Agree. What I meant by the extra flip flop is the one after the counter that pipelines the LOAD control signal. And I see it's a bit different be...
by ijor
Wed Apr 10, 2019 1:38 am
Forum: Hardware
Topic: RAM write wait states
Replies: 36
Views: 2176

Re: RAM write wait states

Yepp, everything is clear now. At the end, LT2 in Verilog: always @(posedge c, negedge xr) begin if (!xr) xq <= 1; else begin xq <= l ? ~dl : ~dc; end end; Not exactly. Load is asynchronous, or more precisely, it seems to be partially synchronous, it is asynchronous in one phase of the clock and sy...
by ijor
Mon Apr 08, 2019 11:10 pm
Forum: 680x0
Topic: Yacht.txt, MOVE to SR, an extra 'np'?
Replies: 6
Views: 574

Re: Yacht.txt, MOVE to SR, an extra 'np'?

TomH wrote:Apologies; clearly I suffered a failure of imagination in not searching for 'YACHT' alone, rather than yacht.txt. That thread is essentially the same question. Will try harder before posting in the future.


No worries. It happens to all of us :)
by ijor
Mon Apr 08, 2019 11:09 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 36
Views: 2176

Re: RAM write wait states

... but on the schematic, it's a latch and not so straightforward for me - the latch gate input gets the inverted value of the clock, that's why I assumed it works on the negative edge. It gets the inverted clock, but that latch is low active. See that the name of the control signal of the latch is...
by ijor
Mon Apr 08, 2019 7:55 pm
Forum: 680x0
Topic: Yacht.txt, MOVE to SR, an extra 'np'?
Replies: 6
Views: 574

Re: Yacht.txt, MOVE to SR, an extra 'np'?

by ijor
Mon Apr 08, 2019 5:38 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 36
Views: 2176

Re: RAM write wait states

Yepp, just all was running on negedge, but the latch holding the load signal (PQ029) operated on positive edge I'm not so familiar with this chip as I am with the ST version, but that doesn't sound right. I think you are misinterpreting the internal clock inversion in the LT2 cell. The clock is inv...
by ijor
Mon Apr 08, 2019 2:02 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 36
Views: 2176

Re: RAM write wait states

I'm running the simulations with interlace = 0 currently. Is it always 1? I'm never 100% sure, just from memory, about the polarity of the signals without double checking. But usually it is trivial to find out the correct polarity under simulation :) Another interesting thing, if I'm right: reset i...
by ijor
Mon Apr 08, 2019 12:40 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 36
Views: 2176

Re: RAM write wait states

Bolding is mine: I don't want to be malicious, but observing a sky in the antique ages led to creating an overcomplicated... geocentric model ;) Don't follow that mistake. If you have the source - analyze it; don't relay on observing only effects if you can access to the mechanism behind them. Of co...
by ijor
Mon Apr 08, 2019 12:32 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 36
Views: 2176

Re: RAM write wait states

D6 = MDE1 or INTERLACE (1) Note that the interlace logic has a bug and interlace is always disabled. See this thread for more details: http://www.atari-forum.com/viewtopic.php?f=15&t=30303 Upd.: assumed the LT2 module changes its output on falling edge. But using rising edge will allow the coun...
by ijor
Mon Apr 08, 2019 1:09 am
Forum: MiSTer
Topic: [Dumb user] Freesync support ?! :-)
Replies: 22
Views: 1258

Re: [Dumb user] Freesync support ?! :-)

[BTW, Freesync is getting kinda standard now, even Nvidia is beginning to support it (in addition or instead of ? G-Sync) ; and it's present on tons of new cheap monitors.] Yes, Freesync is starting to become more mainstream. But note that Nvidia's support is very partial and limited so far. Among ...
by ijor
Mon Apr 08, 2019 1:00 am
Forum: Hardware
Topic: RAM write wait states
Replies: 36
Views: 2176

Re: RAM write wait states

Thanks! I guess it couldn't be more authentic source for information. I'm not sure studying the schematics is the best starting point. Yes, it is probably the most authoritative source. But it will probably be quite difficult to follow and understand, let alone extract the necessary timing informat...
by ijor
Sun Apr 07, 2019 12:18 pm
Forum: MiSTer
Topic: FX CAST Atari ST core
Replies: 195
Views: 41934

Re: FX CAST Atari ST core

I don't see why it would only affect FXCast, as I haven't seen this behavior with any other cores, and I spend many hours in the Amiga and C64 cores. Nevertheless it sounds like I should be using a powered hub anyway, so I have one on order and will do more testing after I get that installed. At le...
by ijor
Sun Apr 07, 2019 12:06 pm
Forum: MiSTer
Topic: [Dumb user] Freesync support ?! :-)
Replies: 22
Views: 1258

Re: [Dumb user] Freesync support ?! :-)

Instead of changing the pixel clock it's possible to change the size of VBlank. I think variable VBlank won't work with HDMI audio. I didn't test this kind of video. Not sure how many monitors support it. That seems to be precisely how Freesync works, changing Vertical Blank duration, even on a fra...
by ijor
Sun Apr 07, 2019 2:50 am
Forum: MiSTer
Topic: [Dumb user] Freesync support ?! :-)
Replies: 22
Views: 1258

Re: [Dumb user] Freesync support ?! :-)

Unlike analog signal, data in HDMI is synced by clock. Very cheap chinese displays happily accept any pixel clock and even fully sync to non standard refresh rates. The only problem with cheap monitors is rubbish quality of panel. Otherwise they would be a perfect monitors for MiSTer. I don't see w...
by ijor
Sat Apr 06, 2019 2:32 pm
Forum: MiSTer
Topic: [Dumb user] Freesync support ?! :-)
Replies: 22
Views: 1258

Re: [Dumb user] Freesync support ?! :-)

Freesync means supporting any refresh rate and pixel clock. Where you got the info that Freesync is that? AFAIK, it is not . As I understand it means a variable refresh rate by adjusting the vertical blank. Pixel clock remains at the standard value. And it requires, or it might require, some negoti...
by ijor
Sat Apr 06, 2019 12:09 pm
Forum: MiSTer
Topic: [Dumb user] Freesync support ?! :-)
Replies: 22
Views: 1258

Re: [Dumb user] Freesync support ?! :-)

I actually think that it would be nice to implement Freesync support. It might allow to achieve the same thing that Vsync does, and even more, but with a method officially supported by the monitors. Unfortunately no of those variable/adaptive refresh rate standards is fully disclosed. I could never ...

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