Search found 27 matches

by sonycman
Thu Dec 05, 2019 6:35 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

it's hard to explain just one line. It's part of whole optimization and migrating CPU to 28MHz domain. Ok. Another recent unmentioned commit was: denise: latch the pixel data later Was that the part of same optimization as well, or another bugfix? Ps: on ultrascale+ this core passes all the timings...
by sonycman
Wed Dec 04, 2019 8:34 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Alexey, recently in sdram_ctrl.v you've had changed CPU chip select signal to composite ramsel: wire ramsel = cpuCS & (~&cpustate | ~cpuU | ~cpuL); I just can't understand why. Did you trying to prevent memory write access when no byte strobes are asserted? Was this change really neccessary?
by sonycman
Mon Dec 02, 2019 11:26 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

I see.
So to test chip ram cache i need to switch to 68020, enable turbochip option and then issue movec #1 to CACR register?

Thanks again, Alexey.
by sonycman
Mon Dec 02, 2019 3:43 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Hello. I want to simulate the CPU cache, integrated in memory controller (file cpu_cache_new.v). I far as i understand, by default it is disabled, so i need to enable it by setting right bits via cpu_cache_ctrl signal? This signal is connected directly to CACR CPU output, so this could be done only ...
by sonycman
Mon Dec 02, 2019 3:36 am
Forum: MiST
Topic: Work on the Minimig core?
Replies: 298
Views: 28049

Re: Work on the Minimig core?

Hello. I want to simulate the CPU cache, integrated in memory controller (file cpu_cache_new.v). I far as i understand, by default it is disabled, so i need to enable it by setting right bits via cpu_cache_ctrl signal? This signal is connected directly to CACR CPU output, so this could be done only ...
by sonycman
Sat Nov 30, 2019 11:18 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

It’s possible to have a very narrow active display. I think I last saw it in the game Flood during loading screens, which gets stretched massively with the Blank+ option. Narrow active area also could be centered in the framebuffer (and thus on the screen) without any manual adjusting, but only if ...
by sonycman
Sat Nov 30, 2019 9:29 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Thanks, Sorgelig. If the blank+ option could accurately guess visible horizontal display area, it would be no problem further to precisely center it in HDMI framebuffer, which makes any hor. position adjusting not needed at all. So that is not the case, am I right? I`am curious because I need to imp...
by sonycman
Thu Nov 28, 2019 2:06 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

I like the look of Blank+ on 4:3, but it is mighty annoying when watching some demos, when the tiny logo suddenly jumps left or right some pixels because the display mode was changed. So what is the difference between the options actually? It seems like the "non-plus" option can display s...
by sonycman
Thu Nov 28, 2019 1:02 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

What would be the best choice for the Video option: Video area by: Blank or Blank+?

I see in the code that blank+ option switches horisontal data enable signal generated directly by bitplanes DMA.
Would that be the preffered and most accurate option?
by sonycman
Mon Nov 25, 2019 9:35 am
Forum: MiST
Topic: Work on the Minimig core?
Replies: 298
Views: 28049

Re: Work on the Minimig core?

Porting minimig on Xilinx currently, and Vivado reported many errors of type: declarations not allowed in unnamed block . Someone has declared local registers under procedural blocks without names. So I had to give names to such a blocks or move the registers outside of them. Is the Quartus okay wit...
by sonycman
Sat Nov 23, 2019 4:31 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

If ramsel is 0 then access is going through chipset which is also wired to SDRAM. So access will be with chipset timings. Oh, thanks! So that direct bus to SDRAM controller from cpu_wrapper is non-existent in the real non-AGA amigas? Hm, but in case of turbo kickstart disabled, CPU would access kic...
by sonycman
Sat Nov 23, 2019 3:44 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Hi, guys. Can somebody give me another little advice on minimig verilog code? How is exactly work turbo-chip and turbo-kick options? I thought they`re just enables the cache for corresponding memory ranges, but now I`am not so sure... Here is the code from cpu_wrapper.v : assign ramsel = cpu_req &am...
by sonycman
Sat Nov 02, 2019 9:27 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Sorgelig wrote:- Scandoubler FX modes including HQ2x.
....
Scandoubler is allowed in interlace mode as well, although it's not supposed to be used in interlace (better to display not a good picture than nothing).

I this scandoubler really necessary when we have the scaler?
Or its for VGA output only?
by sonycman
Fri Nov 01, 2019 9:19 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

kolla wrote:Thanks a lot to everyone for all the improvements on tg68 lately, it really makes a big difference!

Any difference in games?
by sonycman
Sat Sep 21, 2019 8:23 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Should be OK. We only have to disable the 8M and 16M Autoconf Memory boards in tg68k. Zorro III 256MB chunk will be above 24bit address space. I'm not sure if there any apps not able to use >24bit space. Can we redirect Zorro II memory to DDR as well? Funny, with FastRAM in DDR3 only, Sysinfo shows...
by sonycman
Sat Sep 21, 2019 2:19 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

I need an advice too :roll: SDRAM controller slot 2 currently is only for FAST memory accesses (banks other than zero), am I right? Could I remove that slot completely, if the only FAST memory I would use is in DDR? Looks like that didn't hurt much, except it reduces FAST memory by little amount...
by sonycman
Sat Sep 21, 2019 7:21 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Yes, Minimig was slower than it needed to be. But the memory controller performance remaining the same, why the core became slower? Because of the CPU? July's performance increase + September's performance increase. Now Minimig is twice faster. That is cool, i hope that didn't add any stability pro...
by sonycman
Fri Sep 20, 2019 11:49 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Sorgelig wrote:it was lowered in July release.
Later it was raised back to original.

But why?
Something was wrong with the lowered freqs?
by sonycman
Fri Sep 20, 2019 6:20 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

R4MS wrote:
Any idea?

Might be worse now, because of the faster memory access.

But isn't the memory frequency was lowered from 114 to 86 MHz recently? It must be more stable now, not worse.

Which faster memory access do you mean?
by sonycman
Mon Sep 09, 2019 1:17 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Thank you, Alexey, for an overview. Did'nt you use built in minimig scandoubler? I plan to not use any scaler at first, as I seen posts about it causes some flicker on interlaced frames. So 576p is an optimal resolution for me (I'am talking about different board on which I want to port this core, no...
by sonycman
Mon Sep 09, 2019 6:37 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Sorry, its not that easy to write in english for me...

What I wanted to say: amiga low res and high res video modes (scandoubled) should fit in to 576p HDMI resolution.

Super high res with 1280 pixels in horizontal lines needs 720p HDMI.

I'll start with the first two resolutions, as the most used.
by sonycman
Mon Sep 09, 2019 6:13 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Pixel clock is 28 MHz, is'nt it so?
So all it can do is 640x480 or near to it at maximum.

Amiga low resolution mode 320x256 and high resolution 640x256 fits in this good enough.
Don't know much of super high res 1280x256 though.
by sonycman
Mon Sep 09, 2019 5:47 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

Hi guys, It seems that native video output of minimig (VGA) hardcoded to 28 MHz pixel clock, resulting in constant 640x480 (or similar) resolution. Is this correct? If so, could it be possible to send this video stream via HDMI 576p (without the scaler) as nearest resolution? Should the active pixel...
by sonycman
Mon Sep 02, 2019 9:09 am
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

My bad, I counted for the old clock 114 MHz, shame on me :oops: For 86 MHz all seems fine. Why the second slot only accesses non-zero banks? tRC (same bank) after 6 86MHz clocks looking fine (69ns), there is no need for 12 clock delay, so it okay if first and second slots would access the same bank...
by sonycman
Sun Sep 01, 2019 11:19 pm
Forum: MiSTer
Topic: Minimig (Amiga) core discussion
Replies: 1216
Views: 220076

Re: Minimig (Amiga) core discussion

But it seems i've succeeded to reduce amount of cycles in SDRAM controller, so it takes 4 less cycles than before. It allows to switch from 114MHz to 86MHz without touching the 28.6875MHz master clock. In SysInfo the number is 12.70 instead of 12.93 which is not a big loss. 86MHz should give much m...

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