Search found 9 matches

by srg320
Wed Oct 09, 2019 5:28 am
Forum: MiST
Topic: Mister SNES port to MIST possible?
Replies: 237
Views: 22175

Re: Mister SNES port to MIST possible?

arty wrote:Aladdin has huge slowdown with current core test ver13. Please, check it out. I've tested this game with cores ver6,9,10, 12 and gameplay plus demo mode were without additional frame rate loss.

I confirm this issue on MiSTer, it will be fixed soon.
by srg320
Sat Oct 05, 2019 3:25 pm
Forum: MiST
Topic: Mister SNES port to MIST possible?
Replies: 237
Views: 22175

Re: Mister SNES port to MIST possible?

Btw, a test prog for SNES: https://github.com/PeterLemon/SNES/tree/master/SPC700/PlayNoise behaves differently at each reset since the DSP reg randomization. Maybe it doesn't initialize everything, maybe not all registers should be random, don't know. I’m thinking about it, I’ll make a mif file tha...
by srg320
Sat Oct 05, 2019 2:22 pm
Forum: MiST
Topic: Mister SNES port to MIST possible?
Replies: 237
Views: 22175

Re: Mister SNES port to MIST possible?

slingshot wrote:I've added a little optimization to the DSP, seems went wrong.
But without that, the lightgun code didn't fit.

You can try to transfer IPLROM or/and M_TABs to bram.
by srg320
Fri Jul 05, 2019 8:04 am
Forum: MiSTer
Topic: SNES core
Replies: 376
Views: 94509

Re: SNES core

Hi srg320, I have started to look at implementing MSU-1 support to your SNES core: http://helmet.kafuka.org/msu1.htm So far I have setup some code in verilator (SystemVerilog), and begun adding functionality to handle the MSU_ID, MSU_STATUS and MSU_TRACK registers for both read and write. I have al...
by srg320
Sat May 25, 2019 6:02 am
Forum: MiSTer
Topic: SNES core
Replies: 376
Views: 94509

Re: SNES core

@srg320 Do you think maybe in the future you might be interested in adding BSX support? It is the one thing I miss from my SD2SNES, and there are some fun and interesting games for it. I might try it myself someday if you have no interest, but your core is so nice and tidy I hate to mess anything u...
by srg320
Fri May 10, 2019 8:21 am
Forum: MiSTer
Topic: Nintendo 64 and other later Gen Cores
Replies: 11
Views: 3554

Re: Nintendo 64 and other later Gen Cores

IMHO, the main problem is memory.

N64: one chip 9bit @ 500MHz (inside RSP 64+8bit @ 62MHz).
Saturn: many SDRAM chips >= 2Mbit each, max 28 MHz, but with separate buses (2 chips for CPUs, 5 for VDPs, 1 for sound, 1 for CD cpu).

So, can't do without another additional memory.
by srg320
Tue Nov 20, 2018 1:49 pm
Forum: MiSTer
Topic: FPGA SNES source (srg320)
Replies: 52
Views: 9990

Re: FPGA SNES source (srg320)

I plan to use improved SDRAM controller which will provide random access rate equivalent to 10MHz SRAM. Currently it's used only for LHRom mapping and therefore only serves the main CPU. It's definitely enough and more than 3 times faster than CPU needs. But after adding CX4,DSPn,SDD1 will it be en...
by srg320
Tue Nov 20, 2018 10:07 am
Forum: MiSTer
Topic: FPGA SNES source (srg320)
Replies: 52
Views: 9990

Re: FPGA SNES source (srg320)

Sorgelig wrote:Nice to see you here! Do you speak Russian?

Of course.

Sorgelig wrote:What is the working status of cart chips emulation like CX4, DSPn, and others?

CX4, DSPn and SDD1 implemented (are present in sources), but not fully tested. Also, Top gear 3000 (DSP4) has glitches, but I think problem is not in DSPn core.
by srg320
Tue Nov 20, 2018 8:48 am
Forum: MiSTer
Topic: FPGA SNES source (srg320)
Replies: 52
Views: 9990

Re: FPGA SNES source (srg320)

Hello First, sorry for my bad English. To be honest, I never thought that my source will cause so much interest. This is my first big project on FPGA, it is a hobby, not my work, so I hope that experienced FPGA programmers will help me, for this I published a project. The problem is that I have neve...

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