Search found 134 matches

by Smonson
Tue Mar 19, 2019 9:46 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

I'm learning more about small FPGAs at the moment. If I'm in a position to do some experiments in this area I'll let you know how I get along. Right now for me, a lack of time is a big problem.

Maybe this is a project for you?
by Smonson
Mon Mar 18, 2019 11:28 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

But the ST doesn't use a hard-coded palette, so it needs to be a dual-port RAM device. That means two buses going to the FPGA, which is quite a lot of pins at 9-12 bits each. It's something to keep in mind, I guess.
by Smonson
Mon Mar 18, 2019 10:40 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

TotOOntHeMooN wrote:an alternative should be to use a resistors network or a 3x Nbit DAC to input the digital pixels data and output the analog signal.


No need - the ST main board has these already.

TotOOntHeMooN wrote:embed a 256 colours palette to reduce the FPGA design


This would greatly increase the FPGA resources needed.
by Smonson
Mon Mar 18, 2019 10:39 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

EDIT: double post, sorry
by Smonson
Sat Mar 16, 2019 11:03 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

If we're talking about my HDMI mod board - sorry, there's no way to output analogue video from it at this time, because it doesn't have any circuitry to generate the analogue RGB signals. But there's nothing preventing the Verilog code that I've published on github from being used to generate analog...
by Smonson
Sat Mar 16, 2019 10:33 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

You can't actually generate a HDMI picture with 200 lines within the specification... The minimum pixel rate is something like 25MHz, so to generate an image with a small resolution you're supposed to use line-doubling. I'm always using 32MHz for the pixel rate, same as ST mono. For a test, I did im...
by Smonson
Sat Mar 16, 2019 10:01 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

Thanks! Not sure what you mean by the 15KHz signal question. The signal coming in will be the ST's native line frequency (15 or 31KHz) and the output line frequency will always be 31KHz. The picture displayed is either 400 or 480 lines depending on whether borders are shown. 320x200x8 and similar mo...
by Smonson
Wed Feb 06, 2019 7:19 pm
Forum: Chat forum [ENG]
Topic: STart Magazine coverdisks
Replies: 16
Views: 7808

Re: STart Magazine coverdisks

Thank you so much!
by Smonson
Fri Jan 04, 2019 8:11 am
Forum: The Atari 8bit corner
Topic: 2600 mods
Replies: 3
Views: 1474

Re: 2600 mods

I converted mine to SVideo, it's pretty easy and gives about a 1000% picture quality improvement on a modern TV.
by Smonson
Mon Nov 19, 2018 7:58 am
Forum: News & Announcements
Topic: FX68K Cycle accurate 68000 core
Replies: 38
Views: 14428

Re: FX68K Cycle accurate 68000 core

Congratulations Ijor. This completed project surely represents a vast amount of work.
by Smonson
Thu Oct 18, 2018 9:40 am
Forum: Hardware
Topic: STFM to DVI/HDMI project
Replies: 85
Views: 15280

Re: STFM to DVI/HDMI project

Possibly a bit of overbleed from bright pixels into the adjacent ones would also look good? I actually don't own a CRT to study how it really looks.
by Smonson
Thu Oct 18, 2018 9:38 am
Forum: Hardware
Topic: STFM to DVI/HDMI project
Replies: 85
Views: 15280

Re: STFM to DVI/HDMI project

Cyprian wrote:Would be possible to add one feature - scanline mode?


Yep, easy. I've got that planned. Do you think just darkening every second line is the best approach?
by Smonson
Wed Oct 17, 2018 11:38 pm
Forum: Hardware
Topic: STFM to DVI/HDMI project
Replies: 85
Views: 15280

Re: STFM to DVI/HDMI project

A few people are testing prototypes out. I think the next hardware revision will be the first "official" one and I will start making a few of them up for people who want one. Your shifter must be in a socket to be able to install this mod, by the way.
by Smonson
Tue Oct 16, 2018 11:53 am
Forum: Hardware
Topic: STFM to DVI/HDMI project
Replies: 85
Views: 15280

Re: STFM to DVI/HDMI project

Yeah, I can sychronise the line timing to either a long gap between DEs (only for standard modes) or VSYNC. FYI - I have implemented this today. If vsync is connected, then it will use that, otherwise it will use the first DE of each frame as a replacement for vsync. That should make it easier to i...
by Smonson
Wed Oct 03, 2018 8:20 am
Forum: Found Ebay Links
Topic: RARE VINTAGE ATARI 520 STFM COMPUTER
Replies: 15
Views: 2595

Re: RARE VINTAGE ATARI 520 STFM COMPUTER

In Australia, the oft-quoted saying is "...tell him he's dreamin'".
by Smonson
Wed Aug 15, 2018 2:47 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

I didn't test without it, but I had a huge amount of noise on my original prototype (that used stripboard) to the point where it rarely functioned. With the 3.3v clock passing through an unshielded ribbon cable, it seems worth having it. It's only a 40c part, and it's tiny (3x2.5mm), so not too many...
by Smonson
Tue Aug 14, 2018 10:30 pm
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

I'm using a transceiver (74ALVC164245) for the data bus. The 5-to-3.3 shifters are 74LVC245s and the 16MHz clock is buffered at the socket with an MC74VHC1GT125.
by Smonson
Fri Aug 10, 2018 4:38 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

Hmm, I see. I'll leave that problem for later since it seems quite intractable.
by Smonson
Fri Aug 10, 2018 3:01 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

Thanks Troed, I only have the one machine. I'm still not understanding what the problem is though. If the chipset reset skew is related to the MMU/GLUE, then won't it just be another symptom of the wakeup states we already have to compensate for?
by Smonson
Thu Aug 09, 2018 10:53 am
Forum: Hardware
Topic: The SECRET VIDEO MODE in an ST: 400 lines in COLOR (and with 72 Hz)!
Replies: 95
Views: 18469

Re: The SECRET VIDEO MODE in an ST: 400 lines in COLOR (and with 72 Hz)!

...I take back what I said about 320x200x256 being impossible.
by Smonson
Thu Aug 09, 2018 10:28 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

Oh man, I was completely wrong about fitting this into a MAX 7000 CPLD. It does fit into a 100-pin MAX V, but that's the only Altera CPLD architecture supported by Quartus-II that it's able to fit into (421 LEs). They're not 5v devices, and the TQFP-100 is a big package (14x14mm). So to make a stand...
by Smonson
Thu Aug 09, 2018 3:25 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

I haven't published the latest one yet. It's done like this: // Generate 16MHz and 8MHz pixel clocks from 32MHz clock always @(posedge CLOCK_32) begin if (reset) begin speed_divider <= 0; end else begin speed_divider <= speed_divider + 2'b1; end end
by Smonson
Thu Aug 09, 2018 3:21 am
Forum: Hardware
Topic: The SECRET VIDEO MODE in an ST: 400 lines in COLOR (and with 72 Hz)!
Replies: 95
Views: 18469

Re: The SECRET VIDEO MODE in an ST: 400 lines in COLOR (and with 72 Hz)!

Curious, could something be tricked into using this in 640x200(Medium Resolution) but tricking it to Mono for 31khz? Thus eliminating the need for Monitors that support 15khz? If it's 200 colour lines, then it'll only be 15KHz. The 400 mono lines are faster because they only have half the amount of...
by Smonson
Wed Aug 08, 2018 4:22 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

You can measure the wakeup with a Logic Analyzer as I described in the other thread. It is also possible to "visualize" (more or less) the wakeup with a screen that mixes low and med rez. I don't have a logic analyser, so I can't measure it. I have a scope, but that's a pretty unwieldy so...
by Smonson
Wed Aug 08, 2018 3:37 am
Forum: Coding
Topic: SHIFTER reimplementation on FPGA
Replies: 92
Views: 21011

Re: SHIFTER reimplementation on FPGA

But again, you must compare with a real SHIFTER. Some demos do have problems with a real SHIFTER depending on the wakeup. So your implementation is not necessarily wrong. Yeah, I don't think there's a problem with the model, but I like to rule it out. I have no way of seeing which wake-up state the...

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