Search found 2018 matches

by Steven Seagal
Wed Jan 10, 2018 5:56 pm
Forum: Steem
Topic: Steem SSE website is down :(
Replies: 3
Views: 489

Re: Steem SSE website is down :(

Thx but I'd say nothing really important was there, it was mainly a place where successive Steem improvements were presented. I can do that with the blog, it's a suitable format. The other stuff (some games, demos) is widely available elsewhere. The builds and the code are available on sourceforge, ...
by Steven Seagal
Wed Jan 10, 2018 5:44 pm
Forum: Support
Topic: Incorrect screen size in Shadow of the Beast
Replies: 3
Views: 331

Re: Incorrect screen size in Shadow of the Beast

You didn't post your settings but maybe the 'crisp' setting is set and the game displays in medium resolution for a while, that would cause that if that's the biggest possible on that screen.
by Steven Seagal
Mon Jan 08, 2018 9:41 pm
Forum: Steem
Topic: Steem SSE website is down :(
Replies: 3
Views: 489

Re: Steem SSE website is down :(

I deleted it myself, it's briefly explained here:
https://sourceforge.net/p/steemsse/blog

No drama, just adapting to the situation.
For the moment, Steem development is detailed in the same blog, check it out, I didn't post it here because people will accuse me of prematurely bragging.
by Steven Seagal
Sat Jan 06, 2018 8:54 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

I still don't see your point. Hardware is never that precise. Of course that is not N cycles exactly, and the instrument used to measure has its own limitations anyway. But why you do care? This is (mostly) a synchronous design. All that matters is if it is within this, or that cycle. Are you sayin...
by Steven Seagal
Fri Jan 05, 2018 11:18 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

There should be traces I posted long ago. They didn't include the end of the line though, only the start. Must have missed them. I'm not sure what you mean by multiples of 8MHz cycles. Do you mean the relation between each wakestate or the DE-to-LOAD delay? Or what? DL latencies apparently are 3-6 ...
by Steven Seagal
Thu Jan 04, 2018 8:32 pm
Forum: Hardware
Topic: LA traces on interesting video signals
Replies: 27
Views: 938

Re: ST Chipset decap

DE-to-LOAD 3 CPU cycles (WS2) and 6 (WS1) respectively easily seen. Thx, up to now only one such graph was "generally" available I think, and less precise. It seems to be multiples of 8mhz cycles too, I thought there could be some fraction. LOAD is in fact the MMU's DCYC, right? It is sim...
by Steven Seagal
Wed Jan 03, 2018 9:03 am
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

This is what runs the ST-Connexion 4bit scroll in the experimental build of Steem (the traces correspond to the frames). This emulation knows nothing about the technique, it doesn't try to emulate it, it just runs the video logic at the lowest level it can. Maybe 4bit scroll works differently from w...
by Steven Seagal
Mon Jan 01, 2018 11:40 am
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

Thx for interpreting the traces, ijor. First mission of the year, count pixels! I did on the following frames, the scroll is in fact precisely 4 pixels between each frame, there's no 3 pixel scroll between some frames like I thought: stcnx1.png stcnx2.png stcnx3.png stcnx4.png stcnx5.png The corresp...
by Steven Seagal
Sun Dec 31, 2017 5:41 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

I also keep asking the same question over and over. Let's leave it at that, I think there's a misunderstanding about the question.
by Steven Seagal
Sun Dec 31, 2017 5:19 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

No, they're four pixels (else the scroll would not work). The steps are made by leaving 0-3 words in the Shifter, which will cause it to output graphics 0-3 words "earlier" (since the four words fill up faster on the new line). You cannot count cycles as pixels here, the words are discret...
by Steven Seagal
Sun Dec 31, 2017 10:49 am
Forum: Steem
Topic: STEEM SSE Blitter bug
Replies: 19
Views: 1171

Re: STEEM SSE Blitter bug

And after video refactoring I get the exact same bug, so maybe it's something else!
Still investigating.
by Steven Seagal
Sun Dec 31, 2017 10:45 am
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

Well, if you look at the little table I posted you can see my problem. Is the shift visible on the screen 4bit (4 pixels) each step or is there one step of 3 pixels? I figure it's not so easy to see?
by Steven Seagal
Sun Dec 31, 2017 10:08 am
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

maybe some timings are wrong, but were the pixel shifts actually counted? What are you asking? If the scroll worked as described? Yes, it did (does) :) No, if the shifts are certified 4pixels. Do note however that it worked in WS2, WS4, WS3 "50%" and not in WS1 (one offset could not be re...
by Steven Seagal
Sun Dec 31, 2017 9:51 am
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

Below is a seudo simulation waveform of the 4-bit hard scroll. NOTE: the timing is not exact . This is just for the purpose of illustrating the idea of the K offset. Seudo-4bit.png The two vertical guides mark the moment that the resolution changed. First from mono to medium, then to low. Between b...
by Steven Seagal
Sat Dec 30, 2017 11:14 pm
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

Recap: I got the line working in WS1,WS3 and WS4 - always. In WS2 I had two code paths, one that worked in one Shifter wakeup (I guess) and one that worked in the other. On my machines this was migratory, I called them "cold" and "warm". The non-working path produced "every...
by Steven Seagal
Sat Dec 30, 2017 11:10 am
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

This screenshot shows what happens if there is no stabilizer, in this case a R1/R0 switch at the end of the overscan line, neutralized by changing the code of the demo (write 0 instead of 1): no_stab-min.png The traces below show what happens at low level. "PX" marks when the pixel counter...
by Steven Seagal
Fri Dec 29, 2017 10:27 am
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

EDIT Since this post is still there, let's show the traces for the Amiga demo (see below for explanation of PX): 004 - 062:DE1002 070:PX0001 382:DE0302 385:PX0000 512:#00A0 005 - 062:DE1002 070:PX0001 382:DE0302 385:PX0000 419:I0068 512:#00A0 006 - 062:DE1002 070:PX0001 382:DE0302 385:PX0000 512:#00...
by Steven Seagal
Fri Dec 29, 2017 8:38 am
Forum: Coding
Topic: ST Chipset decap
Replies: 125
Views: 22700

Re: ST Chipset decap

Below are simulation waveforms for the above circuit (SHIFTER Reload Control). Showing both correct and incorrect behavior in all three resolutions. ... Note that in all the three resolutions, the incorrect behavior produces Reload pulses 16 pixels later than it should. But the effect is different ...
by Steven Seagal
Thu Dec 28, 2017 9:29 pm
Forum: Hardware
Topic: STFM to DVI/HDMI project
Replies: 78
Views: 4525

Re: STFM to DVI/HDMI project

For "classic" overscan and sync scrolling there is nothing to know. Forget about the original clock mux implementation. Forget about the complicated logic of the pixel counter. Your old, simple, shifter model that you said you implemented before, should work. There is nothing special at a...
by Steven Seagal
Thu Dec 28, 2017 9:11 pm
Forum: Development
Topic: Some patches for the Linux build
Replies: 1
Views: 420

Re: Some patches for the Linux build

Hi,
Thx, unfortunately I've completely let down the Linux build.
Notice that I did nothing special for hi-dpi screens. Did you try the last released version (3.7.2)?
The last version I made Linux-compatible was 382 "pre release", meaning the 3.8.2 code isn't guaranteed.
by Steven Seagal
Thu Dec 28, 2017 9:04 pm
Forum: Support
Topic: Steem SSE 3.9.4 border issues, steem crashes without borders
Replies: 1
Views: 242

Re: Steem SSE 3.9.4 border issues, steem crashes without borders

Hi
Thx for the report.
Couldn't reproduce (no crash for me) but that doesn't mean there's no bug, could trigger only on some systems.
by Steven Seagal
Fri Dec 22, 2017 9:42 pm
Forum: Coding
Topic: Sync-tricks/fullscreen discussion
Replies: 90
Views: 18584

Re: Sync-tricks/fullscreen discussion

ijor wrote:Hmm. Often (even so often) and always are contradictory, aren't they?


"almost always" then :)
by Steven Seagal
Fri Dec 22, 2017 9:02 pm
Forum: Coding
Topic: Sync-tricks/fullscreen discussion
Replies: 90
Views: 18584

Re: Sync-tricks/fullscreen discussion

The CPU strobe pulse can start absolutely on any cycle. It doesn't have to align with any MMU slot. But in practice, since the CPU is so often aligned with the MMU, it should always hit at one or two timings relative to the MMU? For example, a program changing the Shifter palettes with a MOVEM, I e...
by Steven Seagal
Fri Dec 22, 2017 6:06 pm
Forum: Coding
Topic: Sync-tricks/fullscreen discussion
Replies: 90
Views: 18584

Re: Sync-tricks/fullscreen discussion

You don't need half a cycle resolution here because GLUE internally won't care about half a cycle. The CPU data strobe is UDS in this case. RAS/CAS don't reach GLUE and are generated by MMU. Yes, if you make a misaligned write to the rez register, it will alter the timing relation between the chang...
by Steven Seagal
Thu Dec 21, 2017 10:29 pm
Forum: Coding
Topic: Sync-tricks/fullscreen discussion
Replies: 90
Views: 18584

Re: Sync-tricks/fullscreen discussion

To be more precise it's not one cycle, but one and a half cycle. GLUE latches the resolution register at the start of the CPU strobe. But it latches the freq/sync register bits at the end of the strobe. So precise emulation could require using a unit smaller than the CPU cycle. But what is this CPU...

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